Semiconductor device having combined fully associative memories

Abstract

As a TLB (translation look-aside buffer) of a fully associative system is organized, a first CAM (content addressable memory) cell array and a first RAM (random access memory) cell array which together make up one entry are arranged in such a way that they face each other across a control circuit. As a cache memory of a fully associative system is organized, a second CAM cell array and a second RAM cell array which together make up one entry are arranged in such a way that they face each other across the control circuit. Additionally, the second CAM cell array is located next to the first RAM cell array, whereas the second RAM cell array is located next to the first CAM cell array. These four cell arrays make up one section. At the time of a hit in the first CAM cell array, the control circuit enables readout of the first RAM cell array, while it, at the time of a hit of the second CAM cell array, enables readout of the second RAM cell array. Based on logical addresses issued to the first CAM cell array, physical addresses are read from the first RAM cell array. Such physical addresses are supplied to the second CAM cell array as tags for the readout of data from the second RAM cell array.