Matsushita Electric Industrial Co., Ltd.

Matsushita Electronics Corporation

Other

Hirokazu Yonezawa

Seiji Yamaguchi

Satoshi Ishikura

Nobufusa Iwanishi

Yoshiyuki Kawakami

Yasuhiro Tomita

Zhihong Liu

Lifeng Wu

Toshiyuki Shono

Ping F Chen

Norio Koike

Jingkun Fang

Chune-Sin Yeh

Alvin I-Hsien Chen

Takuya Umeda

Initially, non-uniformity of statistical skews between a plurality of clock output terminal pairs is calculated. Next, a partial circuit driven by a clock output terminal pair having each skew distribution is extracted from an integrated circuit. Next, a second statistical timing characteristic which is a maximum value in the partial circuit is obtained from a first statistical timing characteristic of signal paths included in the extracted partial circuit. Next, timing verification for the integrated circuit is performed using the second statistical timing characteristics corresponding to the respective statistical clock skews.

Timing verification method for semiconductor integrated circuit

A statistical delay simulation apparatus includes: a circuit simulator for simulating a circuit operation of a circuit cell constituting an LSI; a statistical delay library generator for driving the circuit simulator and generating, based on a process parameter and the like, a statistical delay library in which the dependency of a delay variation on a predetermined operation condition in each circuit cell is described; a delay calculator for calculating a delay amount of each circuit cell to generate a statistical LSI delay information file containing data on the calculated delay amount; and a static timing analyzer for simulating, based on data of the statistical LSI delay information file, an operation with a delay variation of the LSI to generate a statistical LSI delay analysis result file.

Apparatus for statistical LSI delay simulation

A timing analysis apparatus reads a net list including connection information and the like of circuit cells of an LSI, delay data for previously storing delay information of the circuit cells, stage count-derating factor dependency and components P, V and T of a derating factor; detects the number of stages of each signal path by a signal path cell counting section; determines a derating factor corresponding to the extent of averaging of random variation of each signal path in accordance with the number of stages of the signal path; and performs timing analysis on the basis of the determined derating factor. Therefore, more realistic and highly accurate timing design can be performed on a large-scale circuit.

Timing analysis method and apparatus

After predicting a relationship between a design margin set against a fabrication variation in design of an LSI and a yield, a specific design margin for attaining a given yield is calculated based on the predicated relationship. The yield is a delay yield obtained by cumulating a signal propagation delay time thereby achieving a probability that a signal propagated through a logic circuit of the LSI is delayed by a given amount of time, and the design margin is a derating factor indicating a ratio between the signal propagation delay time and a standard value of the signal propagation delay time.

Method for setting design margin for LSI

There are provided a method for evaluating, in a reduced number of steps, a property of an integrated circuit reflecting operating conditions for an actual LSI and the design of the LSI. The property (delay) of a circuit A (ring oscillator) in a wafer or mounted chip is measured actually or simulated and the property of a circuit B (LSI) is simulated. Then, the interrelation between the degree of property degradation of the circuit A and the degree of property degradation of the circuit B is determined. The circuit property of a circuit AA (ring oscillator) having substantially the same degree of property degradation as the circuit A and manufactured under a new manufacturing condition is measured actually or simulated so that the degree of property degradation of a circuit BB is predicted from the interrelation and the degree of property degradation of the circuit AA. The circuit BB has substantially the same degree of property degradation as the circuit B and is manufactured under a new manufacturing condition.

Method for evaluating property of integrated circuitry

The present invention makes it possible to obtain an aging deterioration margin amount including an allowance for aging deterioration in a simplified manner. Moreover, in order to allow an appropriate inspection taking aging deterioration into account, a delay deterioration rate predicting part outputs signal path delay information before deterioration and signal path delay deterioration rate information for each signal path, based on LSI design information . A delay vs. delay deterioration rate analyzing part outputs delay vs. delay deterioration rate relationship information showing the correlation between the delay and the delay deterioration rate based on the information. A delay deterioration rate extracting part extracts a delay deterioration rate of a predetermined signal path and outputs it as delay deterioration margin . A delay deterioration margin amount calculating part calculates a delay deterioration margin amount by using the delay deterioration margin as a derating factor G. Furthermore, a inspection operation frequency calculating part calculates an operation frequency for inspection using the delay deterioration margin as a derating factor G.

Apparatus and method for calculating temporal deterioration margin amount of LSI, and LSI inspection method

An approach for simulating hot carrier effects in an integrated circuit (IC) at the circuit level includes generating a hot carrier library of delay data for each cell in the IC, using the hot carrier library data to generate a set of scaled timing data for the IC and using the scaled timing data with a IC performance simulator to simulate the IC operation. The scaled timing data is based upon the cell delay data and time-based switching activity of each cell in the IC.

Hot carrier effect simulation for integrated circuits

A circuit extracting apparatus or method of the present invention extracts circuit information which allows a drain current and a gate capacitance in an actual device to be reproduced with high fidelity in circuit simulation. Transistor-portion-configuration recognizing means recognizes the configuration of a transistor portion in the mask layout of a semiconductor circuit so as to generate transistor-portion-configuration data. Transistor-size calculating means calculates an equivalent transistor size based on the transistor-portion-configuration data, such that a drain current in the circuit simulation coincides with the drain current in the actual device. Corrective-capacitance generating means obtains the difference between a gate capacitance in the circuit simulation using the equivalent transistor size and the gate capacitance in the actual device so as to virtually generate a corrective capacitance having a capacitance value corresponding to the obtained difference. The equivalent transistor size and the corrective capacitance serve as the circuit information in the circuit simulation.

Apparatus and method for extracting circuit, system and method for generating information for simulation, and netlist

An apparatus and method of simulating the operation of an LSI after degradation is provided for predicting actual LSI degradation with time at the design stage, so as to prevent the LSI specification from becoming excessively reliable. A reliability library generation device drives a circuit reliability simulator and generates a reliability library which shows the dependence of the property degradation degree of each circuit cell on predetermined operational conditions. A cell delay degradation estimation means estimates the delay degradation degree with time of each circuit cell which composes a target LSI, by referring to the reliability library. An LSI timing degradation estimation means estimates the delay of each circuit cell in the target LSI which has been degraded with time, based on the delay degradation degree of each circuit cell, and generates an after-degradation LSI timing. A logic simulator simulates the operation of an LSI after degradation, based on the after-degradation LSI timing, so that the timing degradation of each signal path in the target LSI can be accurately expressed in conformation to real operation.

Apparatus and method of LSI timing degradation simulation

A data operating circuit in which a logic combinatorial circuit and a transfer gate are built, and a controller for controlling the data operating circuit are disposed. The controller includes a drive unit for applying a drive signal to a gate of an N-channel transistor included in the transfer gate, and a control unit for controlling the operation of the drive unit. The data operating circuit is supplied with a first voltage via a first power supply line, and the controller is supplied with a second voltage that has a higher voltage value than the first voltage. A signal line for transferring an output signal of the data operating circuit to the controller is provided with a level converter for increasing the level of the output signal of the data operating circuit to a level required for the operation of the control unit. As a result, a timing skew of the transfer gate can be retained small while minimizing power consumption of the data operating circuit.

Processor utilizing a low voltage data circuit and a high voltage

As a TLB (translation look-aside buffer) of a fully associative system is organized, a first CAM (content addressable memory) cell array and a first RAM (random access memory) cell array which together make up one entry are arranged in such a way that they face each other across a control circuit. As a cache memory of a fully associative system is organized, a second CAM cell array and a second RAM cell array which together make up one entry are arranged in such a way that they face each other across the control circuit. Additionally, the second CAM cell array is located next to the first RAM cell array, whereas the second RAM cell array is located next to the first CAM cell array. These four cell arrays make up one section. At the time of a hit in the first CAM cell array, the control circuit enables readout of the first RAM cell array, while it, at the time of a hit of the second CAM cell array, enables readout of the second RAM cell array. Based on logical addresses issued to the first CAM cell array, physical addresses are read from the first RAM cell array. Such physical addresses are supplied to the second CAM cell array as tags for the readout of data from the second RAM cell array.

Semiconductor device having combined fully associative memories

A semiconductor memory device has an address translator and a comparator. An entry of the address translator includes an associative memory cell array for storing and comparing a logical address of at least m bits. A first decoder generates a first word signal for the associative memory cell array. A first random access memory cell array stores a physical address of m bits. A controller generates a word signal for the first random access memory cell according to the first word signal and a result of a comparison by the associative memory cell array. A second random access memory cell stores a physical address of m bits. The second random access memory cell is physically disposed near the first random access memory cell array. A second decoder generates a second word signal for the second random access memory cell array. Outputs of the first and second random access memory cell arrays are connected to and compared by the comparator which outputs a signal upon coincidence between the outputs of the first and second random access memory cell arrays.

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Hyogo, Japan

Hirokazu Yonezawa