Kyoto, Japan

Hiroaki Nakaoka

This inventor holds 24 USPTO granted patents, primarily in Semiconductor Fabrication. Top assignee: Matsushita Electric Industrial Co., Ltd.. Active years: 1995-2006.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hiroaki Nakaoka. Retrieved from https://idiyas.com/inventor/hiroaki-nakaoka

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 75.0

Average Co-Inventor Count = 4.1

ph-index = 7

Forward Citations = 158(Granted Patents)


Location History:

  • Katano, JP (1998)
  • Osaka, JP (1995 - 2004)
  • Kyoto, JP (2004 - 2006)
  • Kyotanabe, JP (2006)

Company Filing History:


Years Active: 1995-2006

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Areas of Expertise:
Semiconductor Device
CMOS Transistor
Insulating Film
Doping Method
Vertical Field Effect Transistor
Plasma Bias
Sputter Doping
Evaluation Method
Heat Treatment
Manufacturing Method
Impurity Introduction
Silicon Rich Dielectric
24 patents (USPTO):Explore Patents

Title: The Innovative Contributions of Hiroaki Nakaoka in Semiconductor Technology

Introduction: Hiroaki Nakaoka is a prominent inventor based in Kyoto, Japan, recognized for his significant contributions to the field of semiconductor technology. With an impressive portfolio of 24 patents, he has made remarkable advancements that have influenced modern electronics.

Latest Patents: Nakaoka’s latest patents include groundbreaking technologies designed to enhance semiconductor devices. One of his notable inventions details a method for fabricating semiconductor devices through a unique thermal treatment process. This method involves an initial low-temperature thermal treatment aimed at activating impurities injected into gate electrodes, carefully controlling boron diffusion within polysilicon layers. Following this, a second high-temperature treatment, such as spike annealing, allows for optimized impurity diffusion, achieving superior electronic performance.

Another significant patent involves a method of forming insulating films and fabricating semiconductor devices utilizing plasma bias. By maintaining an oxygen-rich atmosphere within the chamber and applying plasma to a low-temperature wafer, the semiconductor layer can be oxidized into an oxide film without the need for high-temperature thermal oxidation. This innovative approach presents valuable applications in recovering implantation protection films and optimizing surface features before photoresist film removal.

Career Highlights: Hiroaki Nakaoka has dedicated a considerable part of his career to Matsushita Electric Industrial Co., Ltd., where he has been able to apply his expertise in semiconductor technology. His inventive solutions have not only improved device performance but have also contributed to the evolution of fabrication methods in the semiconductor industry.

Collaborations: Throughout his career, Nakaoka has worked alongside notable colleagues such as Atsushi Hori and Takashi Uehara. This collaboration has fostered an innovative environment, enabling the development of several high-impact technologies that pave the way for future advancements in the field.

Conclusion: Hiroaki Nakaoka's contributions to the semiconductor industry reflect his innovative spirit and dedication to advancing technology. His patents, characterized by their unique approaches to semiconductor fabrication and insulation methods, continue to influence the design and manufacturing of electronic devices. As the industry evolves, Nakaoka's work remains foundational, inspiring new innovations in semiconductor applications.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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