The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 07, 2006
Filed:
Feb. 14, 2003
Hisashi Ogawa, Katano, JP;
Hiroaki Nakaoka, Kyotanabe, JP;
Atsuhiro Kajiya, Sanda, JP;
Shin Hashimoto, Hirakata, JP;
Kyoko Egashira, Takaoka, JP;
Hisashi Ogawa, Katano, JP;
Hiroaki Nakaoka, Kyotanabe, JP;
Atsuhiro Kajiya, Sanda, JP;
Shin Hashimoto, Hirakata, JP;
Kyoko Egashira, Takaoka, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
A memory cell transistor and a planar capacitor are provided in a memory region, and both transistors of a CMOS device are provided in a logic circuit region. A capacitance dielectricand a plate electrodeof the planar capacitor are provided over a trench shared with a shallow trench isolationand the upper part of the trench is filled with the capacitance dielectricand the plate electrodeAn n-type diffusion layerthat is a storage node is formed, with an end region thereof extending along one side of the upper part of the trench, to a region of the substrate overlapping with the shallow trench isolationThe area of a part of the substrate functioning as a capacitor can be increased without increasing the substrate area.