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For the Inventor, By the Inventor

Sunnyvale, CA, United States of America

Gideon Intrater

This inventor holds 28 USPTO granted patents and 2 EPO patents, primarily in Memory Devices. Top assignees: Adesto Technologies Corporation, Mips Technologies, Inc., Smsc Holdings Sarl. Active years: 1997-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Gideon Intrater. Retrieved from https://idiyas.com/inventor/gideon-intrater

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 28

% Patents Active = 100.0

 

Average Co-Inventor Count = 2.3

ph-index = 6

Forward Citations = 274(Granted Patents)


Company Filing History:

goldMedal14 out of 129 
 
Adesto Technologies Corporation
 patents
silverMedal7 out of 271 
 
Mips Technologies, Inc.
 patents
bronzeMedal3 out of 58 
 
Smsc Holdings Sarl
 patents
4. 2 out of 4,791 
 
National Semiconductor Corporation
 patents
5. 1 out of 511 
 
Dialog Semiconductor Gmbh
 patents
6. 1 out of 1,092 
 
Globalfoundries U.S. Inc.
 patents
7. 1 out of 2,607 
 
Synopsys, Inc.
 patents
where one patent can have more than one assignee

Years Active: 1997-2025

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Areas of Expertise:
Low Power Standby Mode
Memory Latency Reduction
Concurrent Read Operations
Ultra-Deep Power Down
Cached Memory Structure
Throughput Improvement
SPI Flash Memory
Read Buffers
Software Controlled Power
Processor Extensions
Flash Memory Efficiency
Multi-Processor Debugging
28 patents (USPTO):Explore Patents
1. 12510950 - Low power standby mode for memory devices (2025-12-30),
2. 11704258 - Latency reduction in SPI flash memory devices (2023-07-18),
3. 11681352 - Standby current reduction in memory devices (2023-06-20),
4. 11366774 - Memory latency reduction in XIP mode (2022-06-21),
5. 11094375 - Concurrent read and reconfigured write operations in a memory device (2021-08-17),
6. 10726888 - Read latency reduction in a memory device (2020-07-28),
7. 10636480 - Concurrent read and reconfigured write operations in a memory device (2020-04-28),
8. 10613763 - Memory device having multiple read buffers for read latency reduction (2020-04-07),
9. 10509589 - Support for improved throughput in a memory device (2019-12-17),
10. 10409505 - Ultra-deep power down mode control in a memory device (2019-09-10),
11. 10290334 - Read latency reduction in a memory device (2019-05-14),
12. 10275372 - Cached memory structure and operation (2019-04-30),
13. 10031869 - Cached memory structure and operation (2018-07-24),
14. 9922684 - Memory device ultra-deep power-down mode exit control (2018-03-20),
15. 9812200 - Concurrent read and write operations in a serial flash device (2017-11-07),

Title: The Innovative Journey of Gideon Intrater

Introduction: Gideon Intrater, a visionary inventor based in Sunnyvale, CA, has made significant contributions to the world of technology through his groundbreaking innovations.

Latest Patents: Gideon Intrater holds several patents in the field of artificial intelligence and machine learning, with his most recent patent focusing on advanced robotics for industrial applications.

Career Highlights: With a career spanning over two decades, Gideon has worked for leading tech companies in Silicon Valley, where he played a key role in developing cutting-edge technologies that have revolutionized various industries.

Collaborations: Throughout his career, Gideon has collaborated with top researchers, engineers, and scientists to bring his ideas to life. His collaborative spirit has led to the successful implementation of several game-changing inventions.

Conclusion: Gideon Intrater's passion for innovation and his relentless pursuit of technological advancement continue to inspire the next generation of inventors and entrepreneurs. His impact on the tech industry is truly remarkable, and his legacy will undoubtedly endure for years to come.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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