The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2020

Filed:

May. 02, 2016
Applicant:

Adesto Technologies Corporation, Santa Clara, CA (US);

Inventors:

Gideon Intrater, Sunnyvale, CA (US);

Bard Pedersen, Fremont, CA (US);

Shane Hollmer, Grass Valley, CA (US);

Derric Lewis, Sunnyvale, CA (US);

Stephen Trinh, San Jose, CA (US);

Assignee:

Adesto Technologies Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/419 (2006.01); G11C 8/12 (2006.01); G11C 7/22 (2006.01); G11C 13/00 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); G11C 29/02 (2006.01); G11C 5/14 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 7/22 (2013.01); G11C 8/12 (2013.01); G11C 13/004 (2013.01); G11C 13/0011 (2013.01); G11C 13/0061 (2013.01); G11C 13/0064 (2013.01); G11C 13/0069 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01); G11C 29/021 (2013.01); G11C 29/028 (2013.01); G11C 5/141 (2013.01); G11C 2207/2209 (2013.01); G11C 2211/5623 (2013.01); G11C 2216/22 (2013.01);
Abstract

A method of controlling a memory device can include: receiving, by an interface, a write command from a host; beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of memory cells arranged in a plurality of array planes; receiving, by the interface, a read command from the host; reconfiguring the write operation in response to detection of the read command during execution of the write operation; beginning execution of a read operation on a second array plane in response to the read command; and restoring the configuration of the write operation after the read operation has at least partially been executed.


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