For the Inventor, By the Inventor

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Sunnyvale, CA, United States of America

Adesto Technologies Corporation

USPTO Granted Patents = 129

% Expired Patents = 20.2

EPO Patents = 2

Trademarks = 2

Forward Citations = 658

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57 inventors (with patents filed for the assignee):

Shane Charles Hollmer (31 out of 34 patents)

John Dinh (24 out of 24 patents)

Nad Edward Gilbert (19 out of 20 patents)

4. Bard Pedersen (17 out of 17 patents)

5. Venkatesh P Gopinath (16 out of 58 patents)

6. Foroozan Sarah Koushan (16 out of 24 patents)

7. Gideon Intrater (14 out of 28 patents)

8. Ishai Naveh (13 out of 13 patents)

9. Deepak Kamalanathan (13 out of 14 patents)

10. Derric Lewis (12 out of 12 patents)

11. Narbeh Derhacobian (12 out of 57 patents)

12. Chakravarthy Gopalan (11 out of 16 patents)

13. John Ross Jameson (11 out of 11 patents)

14. Jeffrey Allan Shields (10 out of 83 patents)

15. Yi Ma (9 out of 70 patents)

Core Competencies:

Memory Devices

Resistive Switching

Programmable Impedance

Latency Reduction

Data Retention

Nonvolatile Memory

Read/Write Operations

Dynamic Change

Integrated Circuits

Power Management

Memory Architecture

Signal Processing

129 patents: Sort by Forward Citations

1. 12237857 - Time interleaved phased array receivers (2025-02-25),

2. 12056068 - Memory devices and methods having multiple acknowledgements in response to a same instruction (2024-08-06),

3. 12052039 - Pulse width signal overlap compensation techniques (2024-07-30),

4. 11862749 - Integrated module assembly for optical integrated circuits (2024-01-02),

5. 11705163 - Nonvolatile memory devices, systems and methods with switching charge pump architectures (2023-07-18),

6. 11681352 - Standby current reduction in memory devices (2023-06-20),

7. 11537754 - Pseudo physically unclonable functions (PUFS) using one or more addressable arrays of elements having random/pseudo-random values (2022-12-27),

8. 11392516 - Memory devices and methods having instruction acknowledgement (2022-07-19),

9. 11366774 - Memory latency reduction in XIP mode (2022-06-21),

10. 11107535 - Memory device with adaptive noise and voltage suppression during read-while-write operations (2021-08-31),

11. 11094375 - Concurrent read and reconfigured write operations in a memory device (2021-08-17),

12. 11056646 - Memory device having programmable impedance elements with a common conductor formed below bit lines (2021-07-06),

13. 11056155 - Nonvolatile memory devices, systems and methods with switching charge pump architectures (2021-07-06),

14. 10984861 - Reference circuits and methods for resistive memories (2021-04-20),

15. 10777268 - Static random access memories with programmable impedance elements and methods and devices including the same (2020-09-15),

Company Overview

Adesto Technologies Corporation, based in Sunnyvale, California, specializes in advanced memory devices that leverage innovative technologies such as resistive switching and programmable impedance. The company focuses on enhancing data retention, reducing latency, and optimizing read/write operations in nonvolatile memory solutions. Adesto's expertise in dynamic change positions it as a key player in the evolving landscape of memory technology, catering to diverse applications across various industries.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 20 2026

129 Patents

#40 in Sunnyvale, CA

#677 in California

#3,009 in US

#6,229 in the World

Sunnyvale, CA, United States of America

Adesto Technologies Corporation

Forward Citations = 658

57 inventors:

Shane Charles Hollmer (31 out of 34 patents)

John Dinh (24 out of 24 patents)

Nad Edward Gilbert (19 out of 20 patents)

4. Bard Pedersen (17 out of 17 patents)

5. Venkatesh P Gopinath (16 out of 58 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Adesto Technologies Corporation. Retrieved from https://idiyas.com/company/adesto-technologies

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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