The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 2021

Filed:

Sep. 10, 2019
Applicant:

Adesto Technologies Corporation, Santa Clara, CA (US);

Inventors:

John Dinh, Dublin, CA (US);

Shane Hollmer, Grass Valley, CA (US);

Assignee:

Adesto Technologies Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/26 (2006.01); G11C 7/10 (2006.01); G11C 16/12 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 7/1006 (2013.01); G11C 7/106 (2013.01); G11C 16/12 (2013.01); G11C 2013/0057 (2013.01);
Abstract

A selection circuit includes: a first selection device coupled between a write IO line and a first node; a second selection device coupled between a read IO line and a second node; a third selection device controllable by a first address decode signal, and coupled between a first bit line and a third node; a fourth selection device controllable by a second address decode signal, and coupled between a second bit line and the third node; a first suppression device controllable by a write enable signal, and coupled between the second node and ground; a second suppression device controllable by a read enable signal, and coupled between the first node and ground; a first isolation device controllable by the write enable signal, and coupled between the first and third nodes; and a second isolation device controllable by the read enable signal, and coupled between the second and third nodes.


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