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For the Inventor, By the Inventor

San Jose, CA, United States of America

Ishai Naveh

USPTO Granted Patents = 13

Average Co-Inventor Count = 2.0

ph-index = 4

Forward Citations = 58(Granted Patents)


Company Filing History:

goldMedal13 out of 129 
 
Adesto Technologies Corporation
 patents

Years Active: 2014-2021

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13 patents (USPTO):
1. 10984861 - Reference circuits and methods for resistive memories (2021-04-20),
2. 10726888 - Read latency reduction in a memory device (2020-07-28),
3. 10290334 - Read latency reduction in a memory device (2019-05-14),
4. 9812183 - Read latency reduction in a memory device (2017-11-07),
5. 9755142 - Methods of making memory devices with programmable impedance elements and vertically formed access devices (2017-09-05),
6. 9570166 - Read operations and circuits for memory devices having programmable elements, including programmable resistance elements (2017-02-14),
7. 9373398 - Prototyping integrated circuit devices with programmable impedance elements (2016-06-21),
8. 9343667 - Circuits having programmable impedance elements and vertical access devices (2016-05-17),
9. 8947913 - Circuits and methods having programmable impedance elements (2015-02-03),
10. 8913444 - Read operations and circuits for memory devices having programmable elements, including programmable resistance elements (2014-12-16),
11. 8902631 - Memory devices, circuits and, methods that apply different electrical conditions in access operations (2014-12-02),
12. 8687403 - Circuits having programmable impedance elements (2014-04-01),
13. 8675396 - Integrated circuit devices and systems having programmable impedance elements with different response types (2014-03-18),

Title: The Innovative Contributions of Ishai Naveh

Introduction

Ishai Naveh is a prominent inventor based in San Jose, California. He has made significant contributions to the field of memory devices, holding a total of 13 patents. His work focuses on enhancing the performance and efficiency of resistive memories, which are crucial for modern computing applications.

Latest Patents

Among his latest patents, one notable invention is titled "Reference circuits and methods for resistive memories." This patent describes a memory device that includes multiple memory cells with resistive elements, which can be programmed to switch between different resistance states. The device is designed to store data effectively while utilizing reference cells and circuits to generate reference resistances for accurate data retrieval.

Another significant patent is "Read latency reduction in a memory device." This invention outlines a memory device that features a memory array organized into data lines. It includes an interface for receiving read commands and buffers for storing data lines, which allows for efficient sequential output of data bytes. This innovation aims to minimize read latency, thereby improving the overall performance of memory devices.

Career Highlights

Ishai Naveh is currently employed at Adesto Technologies Corporation, where he continues to develop cutting-edge memory technologies. His expertise in resistive memory systems has positioned him as a key player in the industry, contributing to advancements that enhance data storage and retrieval processes.

Collaborations

Throughout his career, Ishai has collaborated with notable colleagues, including Narbeh Derhacobian and Gideon Intrater. These partnerships have fostered a creative environment that encourages innovation and the development of new technologies in the field of memory devices.

Conclusion

Ishai Naveh's contributions to the field of memory technology are noteworthy, with his patents reflecting a commitment to innovation and efficiency. His work at Adesto Technologies Corporation continues to influence the future of data storage solutions.

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