Adesto Technologies Corporation

Ishai Naveh

Narbeh Derhacobian

Gideon Intrater

Bard Pedersen

Shane Charles Hollmer

Nad Edward Gilbert

Mark T Ramsbey

Venkatesh P Gopinath

Malcolm J Wing

John Dinh

Ravi Sunkavalli

A memory device can include a plurality of memory cells formed in a substrate, each having a resistive element programmable between at least two different resistance states, including memory cells configured to store data received by the memory device, and reference cells; a reference circuit formed in the substrate configured to generate at least a first reference resistance from resistances of a plurality of reference cells; a sense circuit formed in the substrate coupled to the memory cells and at least the first reference resistance and configured to compare a resistance of a selected memory cell to at least the first reference resistance to determine the data stored by the selected memory cell.

Reference circuits and methods for resistive memories

A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a consecutively addressed order from an address of a starting byte; a first buffer that stores a first data line from the memory array that includes the starting byte; a second buffer that stores a second data line from the memory array, which is consecutively addressed with respect to the first data line; output circuitry configured to access data from the buffers, and to sequentially output each byte from the starting byte through a highest addressed byte of the first data line, and each byte from a lowest addressed byte of the second data line until the requested data bytes has been output; and a data strobe driver that clocks each byte of data output by a data strobe on the interface.

Read latency reduction in a memory device

A method can include forming a plurality of access transistors, including forming second semiconductor regions over an integrated circuit substrate that are doped to a second conductivity type, the second semiconductor regions being over and in contact with first semiconductor regions doped to a first conductivity type, and forming third semiconductor regions doped to the first conductivity type in contact with the second semiconductor regions; forming a plurality of conductive structures, over and in contact with the third semiconductor regions; and forming programmable impedance memory cells over and in contact with the conductive structures.

Methods of making memory devices with programmable impedance elements and vertically formed access devices

A memory devices and methods can use multiple sense operations to detect a state of memory elements in a marginal state. In some embodiments, an evaluation circuit can generates an output value for a memory element in response multiple sense results for the same memory element.

Read operations and circuits for memory devices having programmable elements, including programmable resistance elements

A method can include programming programmable resistive elements (PREs) in a first integrated circuit (IC) device to establish functions of configurable circuits of the first IC device; and creating at least one second IC device by forming non-programmable connections based on resistive states of the PREs of the first IC device to provide the functions of the first IC device in the second IC device.

Prototyping integrated circuit devices with programmable impedance elements

A memory device can include at least one programmable impedance cell having at least one programmable layer formed between a first terminal and a second terminal, the programmable layer being programmable between at least two impedance states by application of electric fields; and at least a first access bipolar junction transistor (BJT) coupled to the programmable impedance cell having at least a portion formed by a semiconductor material; wherein a base region and a first emitter region or collector region of the first access BJT are vertically aligned with one another.

Circuits having programmable impedance elements and vertical access devices

Integrated circuit (IC) devices are disclosed that include programmable impedance elements (elements) as data storage element. In some embodiments, IC devices can include latch circuit with one or more elements that establish a function of an associated circuit. In other embodiments, IC devices can include elements arranged in a cross-point array connected to control terminals of access devices. In still other embodiments, a memory device can include a programmable address decoder. Corresponding methods are also disclosed.

Circuits and methods having programmable impedance elements

A memory devices and methods can use multiple sense operations to detect a state of memory elements in a marginal state. In some embodiments, an evaluation circuit can generates an output value for a memory element in response multiple sense results for the same memory element. In other embodiments, a memory device can include both standard and strong read operations, where strong read operations apply more energy to a selected memory element than a standard read operation.

A memory device can include a plurality of physical blocks that each include a number of memory elements programmable between at least two different impedance states, the memory elements being subject to degradation in performance; and bias circuits configured to applying healing electrical conditions to at least one spare physical block that does not contain valid data; wherein the healing electrical conditions are different from write operation electrical conditions, and reverse degradation of the memory elements of the at least one spare physical block.

Memory devices, circuits and, methods that apply different electrical conditions in access operations

An integrated circuit (IC) device may include a first portion having a plurality of volatile memory cells; and a second portion coupled by a data transfer path to the first portion, the second portion including a plurality of nonvolatile memory cells, each nonvolatile memory cell including at least one resistive element programmable more than once between different resistance values. A memory device may also include variable impedance elements accessible by access bipolar junction transistors (BJTs) having at least a portion formed by a semiconductor layer formed over a substrate. A memory device may also include a plurality of memory elements that each includes a dielectric layer formed between a first and second electrode, the dielectric layer including a solid electrolyte with a soluble metal having a mobility less than that of silver in a germanium disulfide.

Circuits having programmable impedance elements

An integrated circuit (IC) device can include a memory array having memory elements formed with a solid ion conductor, the memory array programmable to provide portions with different response types; and a logic section comprising logic circuits configured to perform logic functions, the logic section being coupled to the memory array to store and read data values therefrom. A memory device can also have a plurality of access ports, each configurable to access any of the different portions of the memory array. A memory device can further include a read circuit configured to read data values from the different portions according to the response type of each portion.

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San Jose, CA, United States of America

Ishai Naveh