The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 14, 2017
Filed:
Dec. 16, 2014
Applicants:
Nad Edward Gilbert, Gilbert, AZ (US);
Ishai Naveh, San Jose, CA (US);
Narbeh Derhacobian, Belmont, CA (US);
Inventors:
Nad Edward Gilbert, Gilbert, AZ (US);
Ishai Naveh, San Jose, CA (US);
Narbeh Derhacobian, Belmont, CA (US);
Assignee:
Adesto Technologies Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G11C 11/5614 (2013.01); G11C 13/0011 (2013.01); G11C 2013/0054 (2013.01);
Abstract
A memory devices and methods can use multiple sense operations to detect a state of memory elements in a marginal state. In some embodiments, an evaluation circuit can generates an output value for a memory element in response multiple sense results for the same memory element.
Gilbert, Nad. (2017). Read operations and circuits for memory devices having programmable elements, including programmable resistance elements (U.S. Patent No. 9570166). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9570166
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile