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For the Inventor, By the Inventor

Tokyo, Japan

Fumio Horiguchi

This inventor holds 33 USPTO granted patents, primarily in Semiconductor Memory. Top assignees: Kabushiki Kaisha Toshiba, Tokyo Shibaura Denki Kabushiki Kaisha, Kabushiki Kasiha Toshiba. Active years: 1985-2006.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Fumio Horiguchi. Retrieved from https://idiyas.com/inventor/fumio-horiguchi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 33

% Patents Active = 81.8

Average Co-Inventor Count = 2.6

ph-index = 17

Forward Citations = 1,186(Granted Patents)


Location History:

  • Itabashi, JP (1986)
  • Kawasaki, JP (1989 - 1992)
  • Tokyo-To, JP (2003 - 2005)
  • Tokyo, JP (1985 - 2006)
  • Minato-ku, JP (2006)

Company Filing History:

goldMedal30 out of 53,276 
 
Kabushiki Kaisha Toshiba
 patents
silverMedal2 out of 2,916 
 
Tokyo Shibaura Denki Kabushiki Kaisha
 patents
bronzeMedal1 out of 11 
 
Kabushiki Kasiha Toshiba
 patents

Years Active: 1985-2006

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Areas of Expertise:
Dynamic RAM
Magnetic Random Access Memory
Tunnel Magnetoresistance
Bipolar Transistor
MOS Transistor
High-Density Memory
Charge-Coupling Memory
Integrated Circuit
Manufacturing Process
Storage Node
Memory Device
Trench Type
33 patents (USPTO):Explore Patents
1. 7075820 - Semiconductor memory device for dynamically storing data with channel body of transistor used as storage node (2006-07-11),
2. 7042753 - Multi-value magnetic random access memory with stacked tunnel magnetoresistance (TMR) elements (2006-05-09),
3. 7042040 - Semiconductor device and method for manufacturing the same (2006-05-09),
4. 6891225 - Dynamic semiconductor memory device (2005-05-10),
5. 6548848 - Semiconductor memory device (2003-04-15),
6. 6292390 - Semiconductor device (2001-09-18),
7. 6232822 - Semiconductor device including a bipolar transistor biased to produce a negative base current by the impact ionization mechanism (2001-05-15),
8. 5895946 - MOS random access memory having array of trench type (1999-04-20),
9. 5731609 - MOS random access memory having array of trench type (1998-03-24),
10. 5561311 - Semiconductor memory with insulation film embedded in groove formed on (1996-10-01),
11. 5488242 - Semiconductor memory device (1996-01-30),
12. 5477071 - MOS random access memory having array of trench type (1995-12-19),
13. 5387532 - Semiconductor memory having capacitor electrode formed above bit line (1995-02-07),
14. 5371024 - Semiconductor device and process for manufacturing the same (1994-12-06),
15. 5363325 - Dynamic semiconductor memory device having high integration density (1994-11-08),

Title: Unveiling the Innovations of Fumio Horiguchi

Introduction:

Fumio Horiguchi is a distinguished inventor based in Tokyo, Japan, renowned for his remarkable contributions to the field of semiconductor memory devices.

Latest Patents:

Horiguchi's recent patents showcase his expertise in the development of cutting-edge technologies such as a semiconductor memory device for dynamically storing data with the channel body of a transistor used as a storage node and a semiconductor device and method for manufacturing the same.

Career Highlights:

With an impressive portfolio of 33 patents, Horiguchi has made significant strides in revolutionizing semiconductor technology. His work reflects a deep understanding of MIS transistors and innovative memory cell configurations.

Collaborations:

Throughout his career, Horiguchi has collaborated with esteemed professionals in the industry, including Akihiro Nitayama and Katsuhiko Hieda. His collaborative efforts have led to groundbreaking advancements in semiconductor memory design.

Conclusion:

Fumio Horiguchi's ingenuity and dedication to innovation have solidified his position as a trailblazer in the field of semiconductor technology. His patents continue to shape the future of memory storage devices, leaving a lasting impact on the industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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