Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Kabushiki Kasiha Toshiba

Fumio Horiguchi

Katsuhiko Hieda

Akihiro Nitayama

Fujio Masuoka

Takeshi Hamamoto

Shigeyoshi Watanabe

Kazumasa Sunouchi

Takashi Yamada

Mitsugi Ogura

Takashi Ohsawa

Takehiro Hasegawa

Tsuneaki Fuse

Hiroshi Takato

Koji Sakui

Yoshihisa Iwata

Seiichi Aritome

Yasuo Itoh

Toshiki Seshita

Atsushi Yagishita

Satoshi Inoue

Kei Kurosawa

Shioji Ariizumi

Yoshiaki Asao

Masaki Momodomi

Tohru Ozaki

Kazunori Ohuchi

Hidehiro Watanabe

Naoko Okabe

Satosi Inoue

Kouji Hasimoto

Koji Saku

Mitsugi Oguara

A semiconductor memory device includes a plurality of MIS transistors arranged at intersections of first word lines and bit lines formed on an SOI substrate and each configuring a memory cell. Each of the plurality of MIS transistors includes a channel body formed in a semiconductor layer on an insulating film and set in an electrically floating state, a first extension region formed in contact with the channel body in the semiconductor layer and arranged in a first word line direction, a gate insulating film formed on the channel body, a gate electrode formed on the gate insulating film and electrically connected to a corresponding one of the first word lines, and source and drain regions separately formed in a bit line direction in the semiconductor layer to sandwich the channel body.

Semiconductor memory device for dynamically storing data with channel body of transistor used as storage node

A memory cell is constituted by a TMR element and a MOS transistor. The source diffusion layer of the MOS transistor is connected to a source line and the drain diffusion layer of the transistor is connected to a TMR element via a local interconnection wire. The TMR element is held between the local interconnection wire and a bit line. The TMR element is constituted by stacked TMR layers. Each TMR layer is able to have two states, that is, a state in which spin directions are parallel and anti-parallel. Therefore, the TMR element stores four-value data. A current-driving line is set immediately below the TMR element.

Multi-value magnetic random access memory with stacked tunnel magnetoresistance (TMR) elements

A semiconductor memory device comprises select transistors formed on side surfaces of plural silicon columns defined by a grid-like trenches on a surface of a silicon substrate, each select transistor having a source and a drain on the top surface and the bottom of the silicon column. A capacitor is formed on the top surface of the silicon column to form a DRAM cell. The source/drain layers on the bottom of a greater number of memory cells are commonly connected, or the source/drain layers on the bottom of adjacent memory cells are commonly connected, to be brought out to the surface of the silicon substrate by a connection line to be connected to a constant voltage or a bit line.

Semiconductor device and method for manufacturing the same

A semiconductor memory device comprising: a source diffusion layer formed on a semiconductor substrate and connected to a fixed potential line; a plurality of columnar semiconductor layers arranged in a matrix form and formed on the source diffusion layer and each having one end connected to the source diffusion layer commonly, the columnar semiconductor layer taking a first data state with a first threshold voltage that excessive majority carriers are accumulated in the columnar semiconductor layer, and a second data state with a second threshold voltage that excessive majority carriers are discharged from the columnar semiconductor layer; a plurality of drain diffusion layers each formed at the other end of the columnar semiconductor layer; a plurality of gate electrodes each opposed to the columnar semiconductor layer via a gate insulating film, and connected to the word line; a plurality of word lines each connected to corresponding the gate electrodes; and a plurality of bit lines each connected to corresponding the drain diffusion layers, the bit lines being perpendicular to the word lines.

Dynamic semiconductor memory device

Each of MIS transistors of a semiconductor memory device has a semiconductor layer ( ); a source region ( ) formed in the semiconductor layer; a drain region ( ) formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a channel body in a floating state; a first gate ( ) which forms a channel in the channel body; a second gate ( ) formed so as to control a potential of the channel body by a capacitive coupling; and a high concentration region ( ) formed in the channel body on the second gate side, impurity concentration of the high concentration region being higher than that of the channel body.

Semiconductor memory device

A semiconductor device includes a bipolar transistor whose emitter-collector voltage is set to satisfy a condition I,<I,according to a voltage applied across a base and emitter where I,is the base current flowing through a base-emitter path in a forward direction, and I,is the base current flowing through a collector-base path in a reverse direction.

Semiconductor device

Semiconductor device including a bipolar transistor biased to produce a negative base current by the impact ionization mechanism

A random access memory device includes a semiconductive substrate having a surface in which a groove pattern is formed to provide a plurality of rows and columns of island portions. A plurality of trenches are formed in the island portions, which are provided with an array of memory cells arranged in rows and columns. Each of these memory cells consists of a capacitor and a metal oxide semiconductor (MOS) transistor which are stacked on each other in a corresponding one of the trenches. Parallel word lines are coupled to the rows of memory cells, and parallel bit lines are coupled to the columns of memory cells. An insulative layer is buried in each groove for causing adjacent ones of the island portions to be electrically isolated from each other.

MOS random access memory having array of trench type

A semiconductor memory having memory cells is formed on a semiconductor substrate. Each of the memory cells has a transistor and a capacitor. The transistor includes a channel region, a drain region and a source region aligned in a line and being insulated by an insulation film from an adjacent cell. Each of the memory cells has a gate electrode formed on the channel region with a gate insulating film therebetween. A pad electrode makes electrical contact with one of the source and drain regions of the memory cell and extends over the insulation film. A bit line makes electrical contact with the pad electrode above, extends in parallel to the line and is laterally isolated from one of the source and drain regions. A first insulating film is formed on the semiconductor substrate over the bit line. A first capacitor electrode is formed on the first insulating film, making electrical contact with the other of the source and drain regions of the memory cell through a contact hole opened through the first insulating film and insulated from the bit line by the first insulating film. A second capacitor electrode is formed on the first capacitor electrode with a second insulating film provided therebetween. The insulation film is embedded in a groove formed on the semiconductor substrate.

Semiconductor memory with insulation film embedded in groove formed on

In a DRAM having a structure in which a storage node electrode is formed via an insulator film in a trench formed in a memory cell region to thereby form a capacitor, and in which the storage node electrode is connected in the source/drain regions of a MOSFET through a storage node contact formed in a part of the insulator film, the trench is disposed so as to deviate widthwise in a channel region of the MOSFET, so that the distance between adjacent element regions is reduced without causing misalignment of masks used in the formation of the storage node contact, thereby to provide a miniaturized high-reliability DRAM. In addition, the storage node contact and the trench can be formed in large size.

A semiconductor memory has many memory cells of which each has a transistor and a capacitor. In each memory cell, one of source and drain regions of the transistor is connected to a bit line formed above the transistor. The capacitor includes a first capacitor electrode formed on a substrate and a second capacitor electrode formed on an insulation film coated on the surface of the first capacitor electrode. The first capacitor electrode is connected to the other of the source and drain regions of the transistor. The first capacitor electrode is formed above the bit line. To manufacture such a semiconductor memory, each memory cell region is separately formed on the surface of a substrate. A gate insulation film is formed on the memory cell region. A gate electrode is formed on the gate insulation film. The gate electrode is used as a mask to dope the substrate with impurities to form source and drain regions of a transistor. A bit line is formed and connected to one of the source and drain regions. A first capacitor electrode is formed above the bit line and connected to the other of the source and drain regions. An insulation film is formed on the surface of the first capacitor electrode, and a second capacitor electrode is formed on the insulation film.

Semiconductor memory having capacitor electrode formed above bit line

A semiconductor device has a semiconductor substrate of the first conductivity type, a gate electrode buried in a groove formed in an element region of the substrate, first source and drain regions of the second conductivity type formed in surface regions of the semiconductor substrate on either side of the gate electrode, and second source and drain regions each having a concentration higher than that of each of the first source and drain regions, the second source and drain regions being formed in the surface regions of the semiconductor substrate on either side of the gate electrode, spaced away from the gate electrode, and adjacent to the first source and drain regions, respectively. This semiconductor device has a structure wherein the gate electrode is deeply buried in the substrate. Therefore, a short channel effect can be prevented. The gate electrode buried in the groove extends through the semiconductor region, having a low impurity concentration, formed in the surface region of the semiconductor substrate, and hence two low impurity concentration regions are formed. The source and drain regions respectively consist of a low impurity concentration region and a high impurity concentration region adjacent thereto. The low impurity concentration region allows remarkable improvement of a drain breakdown voltage.

Semiconductor device and process for manufacturing the same

A bipolar transistor Q.sub.1 having a collector formed of a substrate region SUB of a MOS transistor M.sub.1, a base formed of the drain region of the MOS transistor and an emitter formed on the base and connected to a bit line BL is connected between the bit line BL and a memory cell MC formed of the MOS transistor M.sub.1 and and a capacitor C.sub.1 and the current amplifying operation of a bipolar transistor is used for data readout.

Growing community of inventors

Tokyo, Japan

Fumio Horiguchi