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Palo Alto, CA, United States of America

Edgardo F Klass

USPTO Granted Patents = 54 (Patent Applications = 1)

Average Co-Inventor Count = 1.9

ph-index = 9

Forward Citations = 333(Granted Patents)

Forward Citations (Not Self Cited) = 319(Dec 10, 2025)

Inventors with similar research interests:

Location History:

Cupertino, CA (US) (2010 - 2012)
Palo Alto, CA (US) (1998 - 2022)

Company Filing History:

25 out of 7,642

Sun Microsystems, Inc.

23 out of 41,012

P.a. Semi, Inc.

4. 1 out of 832,880

Other

patents

Years Active: 1998-2022

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Areas of Expertise:

Integrated Circuits

Test Pattern Optimization

Dual-Rail Logic

Subthreshold Operation

Voltage Drop Analysis

Failure Rate Reduction

Low Latency Synchronizers

Scan Latch Design

Digital Leakage Detection

Clock Control Mechanisms

Dynamic Flip-Flop Design

Noise Immunity Techniques

54 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 11500019 - Area-aware test pattern coverage optimization (2022-11-15),

2. 11204384 - Methods and systems for switchable logic to recover integrated circuits with short circuits (2021-12-21),

3. 9973191 - Power saving with dual-rail supply voltage scheme (2018-05-15),

4. 9503086 - Lockup latch for subthreshold operation (2016-11-22),

5. 8947070 - Apparatus and method for testing driver writeability strength on an integrated circuit (2015-02-03),

6. 8712752 - IR(voltage) drop analysis in integrated circuit timing (2014-04-29),

7. 8650527 - Method and software tool for analyzing and reducing the failure rate of an integrated circuit (2014-02-11),

8. 8635503 - Scan latch with phase-free scan enable (2014-01-21),

9. 8533645 - Reducing narrow gate width effects in an integrated circuit design (2013-09-10),

10. 8397199 - Versatile method and tool for simulation of aged transistors (2013-03-12),

11. 8341578 - Clock gater with test features and low setup time (2012-12-25),

12. 8332698 - Scan latch with phase-free scan enable (2012-12-11),

13. 8327310 - Method and software tool for analyzing and reducing the failure rate of an integrated circuit (2012-12-04),

14. 8305125 - Low latency synchronizer circuit (2012-11-06),

15. 8301943 - Pulse flop with enhanced scan implementation (2012-10-30),

Title: Edgardo F Klass: Pioneering Inventor from Palo Alto

Introduction: Edgardo F Klass is a renowned inventor based in Palo Alto, California, known for his groundbreaking innovations in various fields.

Latest Patents: Edgardo F Klass holds several patents in the areas of technology, healthcare, and sustainable energy, showcasing his diverse range of expertise.

Career Highlights: With a career spanning over two decades, Edgardo F Klass has consistently pushed the boundaries of innovation, leading to significant advancements in the industry.

Collaborations: Throughout his career, Edgardo F Klass has collaborated with leading tech companies, research institutions, and universities to bring his inventions to life and make a lasting impact on society.

Conclusion: Edgardo F Klass's passion for innovation and his relentless drive to create a better future through his inventions make him a true pioneer in the world of technology.

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