The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 12, 2013
Filed:
Apr. 19, 2010
Apurva H. Soni, Milpitas, CA (US);
Antonietta Oliva, San Jose, CA (US);
Edgardo F. Klass, Palo Alto, CA (US);
Matthew J. T. Page, San Jose, CA (US);
James E. Burnette, Ii, San Jose, CA (US);
Apurva H. Soni, Milpitas, CA (US);
Antonietta Oliva, San Jose, CA (US);
Edgardo F. Klass, Palo Alto, CA (US);
Matthew J. T. Page, San Jose, CA (US);
James E. Burnette, II, San Jose, CA (US);
Apple Inc., Cupertino, CA (US);
Abstract
In an embodiment, an aging analysis tool may be configured to identify transistors that are expected to experience aging effects according to worst case stress vectors and/or designer identified worst case conditions. The aging analysis tool may modify a representation of the circuit (e.g. a netlist), replacing the identified transistors with aged transistors (e.g. by modifying parameters of the transistors in the netlist). The aging analysis tool may process the modified netlist over a range of conditions at which the circuit is expected to operate, to ensure that the design meets specifications after aging. The process may be repeated until the aged design meets specifications (with circuit modifications made by the designer to improve the design).