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Santa Clara, CA, United States of America

P.a. Semi, Inc.

Calculating rank

USPTO Granted Patents = 25

% Expired Patents = 36.0

Forward Citations = 273

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30 inventors (with patents filed for the assignee):

James B Keller (6 out of 120 patents)

Edgardo F Klass (5 out of 54 patents)

Vincent R Von Kaenel (5 out of 61 patents)

4. Sridhar Subramanian (5 out of 52 patents)

5. Po-Yung Chang (4 out of 23 patents)

6. Ruchi Wadhawan (4 out of 34 patents)

7. Rajat Goel (4 out of 6 patents)

8. Ramesh B Gunna (3 out of 47 patents)

9. Brian J Campbell (3 out of 44 patents)

10. Andrew J Demas (3 out of 5 patents)

11. George Kong Yiu (3 out of 10 patents)

12. Greg M Hess (2 out of 42 patents)

13. Daniel C Murray (2 out of 35 patents)

14. Wei-Han Lien (2 out of 35 patents)

15. James Han Wang (2 out of 98 patents)

Core Competencies:

Cache Coherent Communication

Digital Phase Lock Loop

Unified DMA

Integrated Circuit

Voltage-Controlled Oscillator

Memory Array

Digital Jitter Detector

Snoop Operations

Transistor Leakage Detection

Segmented Interconnect

Load/Store Queue

Register File

25 patents: Sort by Forward Citations

1. 7529866 - Retry mechanism in cache coherent communication among agents (2009-05-05),

2. 7500044 - Digital phase relationship lock loop (2009-03-03),

3. 7496695 - Unified DMA (2009-02-24),

4. 7493451 - Prefetch unit (2009-02-17),

5. 7474571 - Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage (2009-01-06),

6. 7472260 - Early retirement of store operation past exception reporting pipeline stage in strongly ordered processor with load/store queue entry retained until completion (2008-12-30),

7. 7461190 - Non-blocking address switch with shallow per agent queues (2008-12-02),

8. 7454674 - Digital jitter detector (2008-11-18),

9. 7426601 - Segmented interconnect for connecting multiple agents in a system (2008-09-16),

10. 7412555 - Ordering rule and fairness implementation (2008-08-12),

11. 7411409 - Digital leakage detector that detects transistor leakage current in an integrated circuit (2008-08-12),

12. 7398361 - Combined buffer for snoop, store merging, load miss, and writeback operations (2008-07-08),

13. 7376817 - Partial load/store forward prediction (2008-05-20),

14. 7373569 - Pulsed flop with scan circuitry (2008-05-13),

15. 7373486 - Partially decoded register renamer (2008-05-13),

Company Overview

P.a. Semi, Inc. is a technology company based in Santa Clara, California, specializing in the design and development of advanced semiconductor solutions. The company focuses on creating high-performance power management integrated circuits and system-on-chip products tailored for various applications, including mobile devices and consumer electronics. With a commitment to innovation, P.a. Semi leverages cutting-edge research in semiconductor technology to enhance energy efficiency and performance in modern electronic systems.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 27 2026

25 Patents

#137 in Santa Clara, CA

#3,162 in California

#13,379 in US

#25,748 in the World

Santa Clara, CA, United States of America

P.a. Semi, Inc.

Forward Citations = 273

30 inventors:

James B Keller (6 out of 120 patents)

Edgardo F Klass (5 out of 54 patents)

Vincent R Von Kaenel (5 out of 61 patents)

4. Sridhar Subramanian (5 out of 52 patents)

5. Po-Yung Chang (4 out of 23 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: P.a. Semi, Inc.. Retrieved from https://idiyas.com/company/p-a-semi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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