The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 18, 2008
Filed:
Jan. 04, 2006
Greg M. Hess, Mountain View, CA (US);
Edgardo F. Klass, Palo Alto, CA (US);
Andrew J. Demas, Los Altos, CA (US);
Ashish R. Jain, Mountain View, CA (US);
Greg M. Hess, Mountain View, CA (US);
Edgardo F. Klass, Palo Alto, CA (US);
Andrew J. Demas, Los Altos, CA (US);
Ashish R. Jain, Mountain View, CA (US);
P.A. Semi, Inc., Santa Clara, CA (US);
Abstract
In one embodiment, a jitter detector comprises a logic circuit coupled to receive a plurality of inputs indicative of states captured from a plurality of outputs of a delay chain responsive to a first clock input and a plurality of clocked storage devices coupled to the logic circuit. The logic circuit is configured to identify a first input of the plurality of inputs that is: (i) captured in error from a corresponding one of the plurality of outputs of the delay chain, and (ii) the corresponding one of the plurality of outputs of the delay chain is least delayed by the delay chain among the plurality of outputs that are captured in error. The plurality of clocked storage devices are configured to accumulate an indication of which of the plurality of outputs have been captured in error over a plurality of clock cycles of the first clock input.