The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 08, 2008
Filed:
Aug. 30, 2005
Ramesh Gunna, San Jose, CA (US);
Po-yung Chang, Saratoga, CA (US);
Sridhar P. Subramanian, Cupertino, CA (US);
James B. Keller, Redwood City, CA (US);
Tse-yuh Yeh, Cupertino, CA (US);
Ramesh Gunna, San Jose, CA (US);
Po-Yung Chang, Saratoga, CA (US);
Sridhar P. Subramanian, Cupertino, CA (US);
James B. Keller, Redwood City, CA (US);
Tse-Yuh Yeh, Cupertino, CA (US);
P.A. Semi, Inc., Santa Clara, CA (US);
Abstract
In one embodiment, an interface unit comprises an address buffer and a control unit coupled to the address buffer. The address buffer is configured to store addresses of processor core requests generated by a processor core and addresses of snoop requests received from an interconnect. The control unit is configured to maintain a plurality of queues, wherein at least a first queue of the plurality of queues is dedicated to snoop requests and at least a second queue of the plurality of queues is dedicated to processor core requests. Responsive to a first snoop request received by the interface unit from the interconnect, the control unit is configured to allocate a first address buffer entry of the address buffer to store the first snoop request and to store a first pointer to the first address buffer entry in the first queue. Responsive to a first processor core request received by the interface unit from the processor core, the control unit is configured to allocate a second address buffer entry of the address buffer to store the first processor core request and to store a second pointer to the second address buffer entry in the second queue.