Sun Microsystems, Inc.

Apple Inc.

P.a. Semi, Inc.

Other

Edgardo F Klass

Chaim Nmi Amir

Bo Tang

Ashish R Jain

Swee Yew Choe

Andrew J Demas

Alan C Rogers

Greg M Hess

Antonietta Oliva

David W Poole

Pradeep R Trivedi

Vincent R Von Kaenel

Brian J Campbell

Gregory Stuart Scott

Shaishav A Desai

Sridhar Narayanan

Anup S Mehta

Priya Ananthanarayanan

Jason M Hart

Peter Smeys

Shih-Chieh Wen

Raymond A Heald

Honkai Tam

Gary R Gouldsberry

Kathirgamar Aingaran

James E Burnette, Ii

Rajat Goel

Ashutosh K Das

Matthew J T Page

Apurva Soni

Chin-Man Kim

Betty Y Lau

Geoffrey M Pilling

In some embodiments, a method may include an area-aware optimization for the test patterns. The method may include dividing the chip area into a grid. The grid may be based on the smallest particle size. The method may include preparing test patterns and identifying a subset of test patterns that touch all of the grid locations. The subset may include a minimum number of test patterns from the prepared test patterns which when implemented exercise the all of the grid locations. The method allows to more quickly determine chips that fail due to extrinsic defects. Once a test fails during the testing process for a chip, testing on the chip is stopped and testing begins on the next chip. Rapidly identifying chips that fail due to extrinsic failures can decrease the overall test time and identify those that will fail quickly as the chip process matures and is dominated by extrinsic failures.

Area-aware test pattern coverage optimization

In some embodiments, a system and/or method may test logic blocks for an integrated circuit. To alleviate problems associated with current methods of integrated circuit testing, a system may include a power switch control signal on a different voltage rail. In some embodiments, a Test VDD may be used to isolate the power switches from the rest of the logic cells in an integrated circuit. During testing, each logic block may be powered individually using the Test VDD to control the power switches to the logic blocks. When a logic block short is identified, the nonviable logic block may be isolated to such that the nonviable logic block is not used during the future and only viable logic blocks are used in the integrated circuit. This allows for use of logic within an integrated circuit that might otherwise have been discarded or destroyed because of one or more shorts.

Methods and systems for switchable logic to recover integrated circuits with short circuits

In an embodiment, an integrated circuit includes a clock tree circuit and logic circuitry that is clocked by the clocks received from the clock tree circuit. The logic circuit is powered by a first power supply voltage. The integrated circuit includes a voltage regulator that receives the first power supply voltage and generates a second power supply voltage having a magnitude that is lower than the magnitude of the first power supply voltage by a predetermined amount. The second power supply voltage may track the first power supply voltage over dynamic changes during use, either intentional changes to operating state or noise-induced changes. The second power supply voltage may be used to power at least a portion of the clock tree.

Power saving with dual-rail supply voltage scheme

In an embodiment, an integrated circuit may include edge triggered flops that launch data to start a clock cycle and that capture data at the end of the clock cycle. Combinatorial logic circuitry may be coupled between the launching and capturing flops, and may be configured to operate on the launched data to generate result data for the capturing flops. One or more latches may be provided in the combinatorial logic circuitry, which may close and capture intermediate values responsive to an opposite edge of the clock than the edge that triggers the edge-triggered flops. In an embodiment, the clock to the latches may be gated with an enable. When the integrated circuit is not operating in the subthreshold voltage region, the enable may be in the disabled state. When operating in the subthreshold voltage region, the enable may be in the enabled state.

Lockup latch for subthreshold operation

An apparatus and method for testing driver write-ability strength on an integrated circuit includes one or more drive detection units each including a number of drivers. At least some of the drivers may have a different drive strength and each may drive a voltage onto a respective driver output line. Each drive detection unit may include a number of keeper circuits, each coupled to a separate output line and configured to retain a given voltage on the output line to which it is coupled. Each detection unit may also include a number of detection circuits coupled to detect the drive voltage on each of the output lines. In one implementation, the drive voltage appearing at the output line of each driver may be indicative of that the driver was able to overdrive the voltage being retained on the output line to which it is coupled by the respective keeper circuits.

Apparatus and method for testing driver writeability strength on an integrated circuit

In one embodiment, an IR drop analysis methodology may include characterizing standard cells without including power parasitic impedances, extracting the power parasitic impedances for the standard cells, and characterizing the standard cells with the power parasitic impedances. A set of timing parameters (such as minimum delays and maximum delays through the cells) may be generated from each characterization. The methodology may include comparing the timing parameters from each characterization, and identifying cells for which additional design effort should be expended to improve the power supply grid (e.g. to reduce the power parasitic impedances). For example, a margin may be budgeted for speed loss (delay increase) due to IR drop. If the difference in the timing parameters exceeds the margin, additional design effort may be warranted.

IR(voltage) drop analysis in integrated circuit timing

A software tool and method for analyzing the reliability or failure rate of an integrated circuit (IC) are disclosed. The IC may include a plurality of circuit designs, and the software tool and method may aid a designer of the IC in determining a reliability rating of the IC based on reliability ratings of transistors or other circuit devices used in the circuit designs. In particular, the IC may include one or more circuit designs that have multiple instances within the IC (i.e., the same circuit design is instantiated multiple times), and the software tool and method may take into account the multiple instances when determining the reliability rating of the IC.

Method and software tool for analyzing and reducing the failure rate of an integrated circuit

A number of scan flops clocked by a master clock may be used to constructing a scan chain to perform scan tests. During a scan test, data appearing at the regular data input of each scan flop may be written into a master latch of the scan flop during a time period when the scan control signal is in a state corresponding to a capture cycle. A slave latch in each scan flop may latch a value appearing at the regular data input of the scan flop according to a narrow pulse triggered by the rising edge of the master clock when the scan control signal is in the state corresponding to the capture cycle. The slave latch may latch the data provided by the master latch according to a wide pulse triggered by the rising edge of the master clock when the scan control signal is in a state corresponding to a shift cycle. This may permit toggling the scan control signal during either a high phase or a low phase of the master clock, and may also enable testing the pulse functionality of each scan flop.

Scan latch with phase-free scan enable

A method for reducing narrow gate width effects in an integrated circuit includes finding the smallest transistor channel widths that are larger than the minimum width for the technology for library cells that produce logic blocks that meet timing constraints while using the least amount of power and have the smallest possible area. The method may include characterizing a device library while varying process, voltage and temperature parameters, and synthesizing an HDL representation of a functional logic block including cells from the device library. The method may also include determining whether timing, area, and power values of the functional logic block are within a predetermined range. In response to the timing, area, and power values not being within the predetermined range, iteratively increasing the channel width of at least a portion of the transistors of at least one of the cells in the device library.

Reducing narrow gate width effects in an integrated circuit design

In an embodiment, an aging analysis tool may be configured to identify transistors that are expected to experience aging effects according to worst case stress vectors and/or designer identified worst case conditions. The aging analysis tool may modify a representation of the circuit (e.g. a netlist), replacing the identified transistors with aged transistors (e.g. by modifying parameters of the transistors in the netlist). The aging analysis tool may process the modified netlist over a range of conditions at which the circuit is expected to operate, to ensure that the design meets specifications after aging. The process may be repeated until the aged design meets specifications (with circuit modifications made by the designer to improve the design).

Versatile method and tool for simulation of aged transistors

A clock gater circuit comprises a plurality of transistors having source-drain connections forming a stack between a first node and a supply node. A given logical state on the first node causes a corresponding logical state on an output clock of the clock gater circuit. In one embodiment, a first transistor of the plurality of transistors has a gate coupled to receive an enable input signal. A second transistor is connected in parallel with the first transistor, and has a gate controlled responsive to a test input signal to ensure that the output clock is generated even if the enable input signal is not in an enabled state. In another embodiment, the plurality of transistors comprises a first transistor having a gate controlled responsive to a clock input of the clock gater circuit and a second transistor having a gate controlled responsive to an output of a delay circuit. The delay circuit comprises at least one inverter, wherein an input of the delay circuit is the clock input, and wherein a first inverter of the delay circuit is coupled to receive a test input signal and is configured to force a first logical state on an output of the first inverter responsive to an assertion of the test input signal.

Clock gater with test features and low setup time

A synchronizer circuit includes a master stage and a slave stage. The master stage may include a first master latch coupled to receive a data input signal, and a clock signal. The master stage may also include a second master latch coupled to receive the data input signal, and a delayed version of the clock signal. The master stage may further include a pull-up circuit that may drive an output line of the master stage depending upon an output of each of the first master latch and the second master latch. The slave stage may include a slave latch having an input coupled to the output line of the master stage. The slave stage may provide an output data signal that corresponds to the captured input data signal and is synchronized to the receiving clock signal.

Low latency synchronizer circuit

In an embodiment, a clocked storage device such as a pulse flop is provided. The pulse flop includes a latch coupled to receive a scan data input to the pulse flop. The latch receives the scan data input during one of the phases of the clock, and retains the received input during the other phase. The other phase is the phase in which the pulse to the pulse flop occurs. Thus, when scan data is captured in the pulse flop, the latch at the next pulse flop in the chain may be closed and may prevent a race condition in propagating the scan data.

Growing community of inventors

Palo Alto, CA, United States of America

Edgardo F Klass