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For the Inventor, By the Inventor

Verl, Germany

Dominik Lubeley

This inventor holds 21 USPTO granted patents and 10 published patent applications and 11 EPO patents, primarily in FPGA Programming. Top assignees: Dspace Gmbh, Dspace Digital Signal Processing and Control Engineering Gmbh. Active years: 2017-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Dominik Lubeley. Retrieved from https://idiyas.com/inventor/dominik-lubeley

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 21 

% Patents Active = 100.0

 

Average Co-Inventor Count = 2.3

ph-index = 2

Forward Citations = 6(Granted Patents)


Location History:

  • Verl, DE (2017 - 2023)
  • Paderborn, DE (2021 - 2024)

Company Filing History:

goldMedal11 out of 92 
 
Dspace Gmbh
 patents
silverMedal10 out of 166 
 
Dspace Digital Signal Processing and Control Engineering Gmbh
 patents

Years Active: 2017-2026

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Areas of Expertise:
FPGA Configuration
Bitwidth Change
Memory Increase
Data Communication
Signal Sampling
Hierarchical Block Diagram
Distributed Simulation
Power Consumption
Netlist Generation
Programmable Logic Device
Graph-Based Similarity
Troubleshooting Logic
21 patents (USPTO):Explore Patents
1. 12639500 - Method of adding another circuit component (2026-05-26),
2. 12348236 - Method for changing a bitwidth of an FPGA configuration (2025-07-01),
3. 12341512 - Method for programming an FPGA (2025-06-24),
4. 12265771 - Method for dividing simulation models up between a processor and an FPGA (2025-04-01),
5. 12253876 - Method for programming an FPGA (2025-03-18),
6. 12197336 - Method for effectively increasing a memory on an FPGA (2025-01-14),
7. 12158849 - Method for data communication between subregions of an FPGA (2024-12-03),
8. 12124290 - Time-synchronized input and/or output of signals with a selectable sampling rate (2024-10-22),
9. 12079601 - Computer-implemented method for creating a hierarchical block diagram (2024-09-03),
10. 11843514 - Computer-implemented method for restructuring a predefined distributed real-time simulation network (2023-12-12),
11. 11586793 - Method for producing an association list (2023-02-21),
12. 11442884 - Method for programming a programmable gate array in a distributed computer system (2022-09-13),
13. 11222159 - Method, computer-based system and computer program product for planning partitions for a programmable gate array (2022-01-11),
14. 11187748 - Procedure for reviewing an FPGA-program (2021-11-30),
15. 11017141 - Method for troubleshooting the program logic of a system of distributed progammable gate arrays (2021-05-25),

Title: Inventor Dominik Lubeley

Introduction: Dominik Lubeley is a renowned inventor hailing from Verl, Germany. His innovative spirit and dedication to creating groundbreaking solutions have earned him a notable reputation in the field of technology.

Latest Patents: Dominik Lubeley holds several patents in various technological domains, showcasing his versatility and ingenuity in inventing novel solutions to complex problems.

Career Highlights: Throughout his career, Dominik Lubeley has consistently pushed the boundaries of innovation, contributing significantly to the advancement of technology. His work has not only garnered recognition but has also made a tangible impact on industries worldwide.

Collaborations: Dominik Lubeley has collaborated with leading tech companies and research institutions, leveraging his expertise to drive forward cutting-edge projects. His collaborative efforts have resulted in the development of revolutionary technologies that have reshaped the technological landscape.

Conclusion: Dominik Lubeley's passion for innovation and his relentless pursuit of excellence continue to inspire aspiring inventors and shape the future of technology. His contributions to the field will undoubtedly leave a lasting legacy in the world of inventions.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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