The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2025

Filed:

May. 09, 2022
Applicant:

Dspace Gmbh, Paderborn, DE;

Inventors:

Heiko Kalte, Paderborn, DE;

Dominik Lubeley, Paderborn, DE;

Assignee:

dSPACE GMBH, Paderborn, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/331 (2020.01); G06F 30/3312 (2020.01); H03K 19/17736 (2020.01); H03K 19/1776 (2020.01); H03K 19/17792 (2020.01);
U.S. Cl.
CPC ...
H03K 19/17792 (2013.01); H03K 19/1774 (2013.01); H03K 19/17744 (2013.01); H03K 19/1776 (2013.01);
Abstract

A method for programming an FPGA, wherein a library, which includes elementary operations and a particular latency table for each of the elementary operations of the library is provided. Each latency table indicates the latency of the particular operation for a plurality of clock rates of the FPGA and for a plurality of input bit widths of the particular operation during the execution on the FPGA, depending on the input bit width of the particular operation and the clock rate of the FPGA. A data path indicating a consecutive execution of at least two elementary operations of the library on the FPGA is defined. The latencies given for the particular input bit width of the particular elementary operations of the data path for a plurality of different clock rates in the latency tables are detected and added, then one of the clock rates is selected.


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