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For the Inventor, By the Inventor

Pflugerville, TX, United States of America

Dharmendar Reddy Palle

This inventor holds 22 USPTO granted patents and 1 published patent application. Top assignees: Samsung Electronics Co., Ltd., The University of Texas System. Active years: 2012-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Dharmendar Reddy Palle. Retrieved from https://idiyas.com/inventor/dharmendar-reddy-palle

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 22 

% Patents Active = 81.8

Average Co-Inventor Count = 4.6

ph-index = 5

Forward Citations = 143(Granted Patents)


Location History:

  • Pflugerville, TX (US) (2016)
  • Bellevue, WA (US) (2020)
  • Austin, TX (US) (2012 - 2024)

Company Filing History:

goldMedal20 out of 132,108 
 
Samsung Electronics Co., Ltd.
 patents
silverMedal2 out of 5,633 
 
The University of Texas System
 patents

Years Active: 2012-2024

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22 patents (USPTO):Explore Patents
1. 12080703 - Semiconductor cell blocks having non-integer multiple of cell heights (2024-09-03),
2. 11556768 - Optimization of sparsified neural network layers for semi-digital crossbar architectures (2023-01-17),
3. 11552067 - Semiconductor cell blocks having non-integer multiple of cell heights (2023-01-10),
4. 11475933 - Variation mitigation scheme for semi-digital mac array with a 2T-2 resistive memory element bitcell (2022-10-18),
5. 11217392 - Composite piezoelectric capacitor (2022-01-04),
6. 11182686 - 4T4R ternary weight cell with high on/off ratio background (2021-11-23),
7. 11101320 - System and method for efficient enhancement of an on/off ratio of a bitcell based on 3T2R binary weight cell with spin orbit torque MJTs (SOT-MTJs) (2021-08-24),
8. 10872662 - 2T2R binary weight cell with high on/off ratio background (2020-12-22),
9. 10832774 - Variation resistant 3T3R binary weight cell with low output current and high on/off ratio (2020-11-10),
10. 10566330 - Dielectric separation of partial GAA FETs (2020-02-18),
11. 10205025 - Methods to achieve strained channel finFET devices (2019-02-12),
12. 10181527 - FinFet having dual vertical spacer and method of manufacturing the same (2019-01-15),
13. 9978833 - Methods for varied strain on nano-scale field effect transistor devices (2018-05-22),
14. 9905672 - Method of forming internal dielectric spacers for horizontal nanosheet FET architectures (2018-02-27),
15. 9871139 - Sacrificial epitaxial gate stressors (2018-01-16),

Title: The Innovative Journey of Dharmendar Reddy Palle

Introduction: Dharmendar Reddy Palle, a talented inventor based in Pflugerville, TX, has made significant contributions to the field of technology through his creative innovations and patented inventions.

Latest Patents: Dharmendar Reddy Palle's latest patents include groundbreaking inventions in the realm of artificial intelligence and renewable energy technologies, showcasing his commitment to driving progress in these crucial areas.

Career Highlights: With a career spanning over two decades, Dharmendar Reddy Palle has established himself as a visionary inventor with a keen eye for identifying gaps in the market and developing solutions that address pressing challenges. His innovative spirit has led to the successful commercialization of several patented technologies.

Collaborations: Throughout his career, Dharmendar Reddy Palle has collaborated with leading research institutions, universities, and tech companies to further enhance the impact of his inventions. These collaborations have not only accelerated the development process but have also opened up new avenues for future innovations.

Conclusion: Dharmendar Reddy Palle's relentless pursuit of innovation and his passion for creating technologies that make a difference have solidified his reputation as a respected inventor in the industry. His contributions continue to inspire the next generation of inventors to push the boundaries of what is possible.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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