Samsung Electronics Co., Ltd.

University of Texas System

Dharmendar Reddy Palle

Joon Goo Hong

Mark Stephen Rodder

Jorge A Kittl

Rwik Sengupta

Titash Rakshit

Ryan M Hatcher

Borna Josip Obradovic

Sanjay K Banerjee

Robert Christopher Bowen

Emanuel Tutuc

Vassilios Gerousis

Leonard Franklin Register, Ii

Allan MacDonald

Kevin Michael Traynor

Tanya Abaya

Wei-E Wang

Mohammad Ali Pourghaderi

A semiconductor cell block includes a series of layers arranged in a stack. The layers include one or more first layers each having a first height and one or more second layers each having a second height. The second height is larger than the first height, and the second height is a non-integer multiple of the first height. The semiconductor cell block also includes a first semiconductor logic cell having a first cell height in one of the series of layers, and a second semiconductor logic cell having a second cell height in one of the series of layers. The second cell height is larger than the first cell height, and the second cell height is a non-integer value multiple of the first cell height.

Semiconductor cell blocks having non-integer multiple of cell heights

A method and system are provided. The method includes mapping a binary matrix to an undirected graph form, applying a two-way graph partition algorithm to the mapped binary matrix that minimizes edge cuts between partitions in the mapped binary matrix, applying a greedy algorithm recursively to find a set of row or column permutations that maximizes a transfer of non-zeros from sparse blocks to nonsparse blocks, and sparsifying or densifying the binary matrix according to the applied greedy algorithm.

Optimization of sparsified neural network layers for semi-digital crossbar architectures

A method, system and electronic device for mitigating variance in a two transistor two resistive memory element (2T2R) circuit is provided. The method includes calculating a sum of a number of logical 1's in a column of bitcells in the 2T2R circuit, N, of an input vector, sensing output current values from each current line in the column of bitcells and calculating an inner product, M, of the input vector and the bitcells in the column in the 2T2R circuit based on the sensed output current values.

Variation mitigation scheme for semi-digital mac array with a 2T-2 resistive memory element bitcell

A circuit element. In some embodiments, the circuit element includes a first terminal, a second terminal, and a layered structure. The layered structure may include a first conductive layer connected to the first terminal, a first piezoelectric layer on the first conductive layer, a second piezoelectric layer on the first piezoelectric layer, and a second conductive layer connected to the second terminal. The first piezoelectric layer may have a first piezoelectric tensor and a first permittivity tensor, and the second piezoelectric layer may have a second piezoelectric tensor and a second permittivity tensor, one or both of the second piezoelectric tensor and a second permittivity tensor differing, respectively, from the first piezoelectric tensor and the first permittivity tensor.

Composite piezoelectric capacitor

A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET being connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET, a third FET and a third resistive memory element connected to a drain of the third FET, and a fourth FET and a fourth resistive memory element connected to a drain of the fourth FET, the drain of the third FET is connected to a gate of the fourth FET and the drain of the fourth FET being connected to a gate of the third FET.

4T4R ternary weight cell with high on/off ratio background

A weight cell, an electronic device and a device are provided. The weight cell includes a first resistive memory element and a second resistive memory element, a select transistor, and a layer of Spin Hall (SH) material disposed between the first resistive memory element and the second resistive memory element, the layer of the SH material including a first contact and a second contact. The first contact of the SH material is connected to a drain of the select transistor and the second contact of the SH material is connected to an external word line.

System and method for efficient enhancement of an on/off ratio of a bitcell based on 3T2R binary weight cell with spin orbit torque MJTs (SOT-MTJs)

A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, and a second FET and a second resistive memory element connected to a drain of the second FET. The drain of the first FET is connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET.

2T2R binary weight cell with high on/off ratio background

A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET is connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET, and a third FET, and a load resistor connected to a drain of the third FET.

Variation resistant 3T3R binary weight cell with low output current and high on/off ratio

A CMOS system on chip including a series of partial gate-all-around field effect transistors. Each partial GAA FET includes a fin having a stack of channel regions, source and drain regions on opposite sides of the fin, a dielectric separation region including a dielectric material between first and second channel regions, a gate stack on the fin, and a pair of sidewall spacers on opposite sides of the gate stack. A portion of the dielectric separation region has a length from an outer edge of the dielectric separation region to an inner edge of a respective sidewall spacer. The length of the portion of the dielectric separation region of one of the partial GAA FETs is different than the length of the portion of the dielectric separation region of another one of the partial GAA FETs.

Dielectric separation of partial GAA FETs

Methods to achieve strained channel finFET devices and resulting finFET devices are presented. In an embodiment, a method for processing a field effect transistor (FET) device may include forming a fin structure comprising a fin channel on a substrate. The method may also include forming a sacrificial epitaxial layer on a side of the fin structure. Additionally, the method may include forming a deep recess in a region that includes at least a portion of the fin structure, wherein the fin structure and sacrificial layer relax to form a strain on the fin channel. The method may also include depositing source/drain (SD) material in the deep recess to preserve the strain on the fin channel.

Methods to achieve strained channel finFET devices

A field effect transistor (FET) structure includes: a gate; a first spacer having a first dielectric constant at a first region adjacent to the gate; and a second spacer having a second dielectric constant that is greater than the first dielectric constant at a second region adjacent to the gate.

FinFet having dual vertical spacer and method of manufacturing the same

A semiconductor device and a method to form the semiconductor device are disclosed. An n-channel component of the semiconductor device includes a first horizontal nanosheet (hNS) stack and a p-channel component includes a second hNS stack. The first hNS stack includes a first gate structure having a plurality of first gate layers and at least one first channel layer. A first internal spacer is disposed between at least one first gate layer and a first source/drain structure in which the first internal spacer has a first length. The second hNS stack includes a second gate structure having a plurality of second gate layers and at least one second channel layer. A second internal spacer is disposed between at least one second gate layer and a second source/drain structure in which the second internal spacer has a second length that is greater than the first length.

Methods for varied strain on nano-scale field effect transistor devices

A method to form a nanosheet stack for a semiconductor device includes forming a stack of a plurality of sacrificial layers and at least one channel layer on an underlayer in which a sacrificial layer is in contact with the underlayer, each channel layer being in contact with at least one sacrificial layer, the sacrificial layers are formed from SiGe and the at least one channel layer is formed from Si; forming at least one source/drain trench region in the stack to expose surfaces of the SiGe sacrificial layers and a surface of the at least one Si channel layer; and oxidizing the exposed surfaces of the SiGe sacrificial layers and the exposed surface of the at least one Si layer in an environment of wet oxygen, or ozone and UV.

Method of forming internal dielectric spacers for horizontal nanosheet FET architectures

A method for fabricating a fin field effect transistor (finFET) device with a strained channel. During fabrication, after the fin is formed, a sacrificial epitaxial gate stressor is deposited on the fin, causing strain in the fin. SD structures are then formed to anchor the ends of the fin, and the sacrificial epitaxial gate stressor is removed.

Growing community of inventors

Pflugerville, TX, United States of America

Dharmendar Reddy Palle