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For the Inventor, By the Inventor

Hsinchu, Taiwan

Chin Kun Lan

This inventor holds 18 USPTO granted patents and 4 published patent applications, primarily in Semiconductor Technology. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2002-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chin Kun Lan. Retrieved from https://idiyas.com/inventor/chin-kun-lan

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 18 

% Patents Active = 88.9

Average Co-Inventor Count = 2.4

ph-index = 3

Forward Citations = 39(Granted Patents)


Location History:

  • Taichung, TW (2002)
  • Hsin-Chu, TW (2003 - 2024)

Company Filing History:

goldMedal18 out of 42,965 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents

Years Active: 2002-2025

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Areas of Expertise:
Semiconductor Structure
High Breakdown Voltage
Etch-Stop Layer
MRAM Spacer Scheme
Magnetic Tunnel Junctions
Multi-Layer Mask
Inter-Metal Dielectric
Diffusion Region Routing
Oxygen Plasma Reduction
Planarization
Shallow Trench Isolation
Silicon Nitride Delamination
18 patents (USPTO):Explore Patents
1. 12315812 - Semiconductor structure having high breakdown voltage etch-stop layer (2025-05-27),
2. 12310257 - Spacer scheme and method for MRAM (2025-05-20),
3. 12268096 - Spacer stack for magnetic tunnel junctions (2025-04-01),
4. 11961803 - Semiconductor structure having high breakdown voltage etch-stop layer (2024-04-16),
5. 11818964 - Spacer scheme and method for MRAM (2023-11-14),
6. 11785858 - Methods for forming a spacer stack for magnetic tunnel junctions (2023-10-10),
7. 11769692 - High breakdown voltage inter-metal dielectric layer (2023-09-26),
8. 11488825 - Multi-layer mask and method of forming same (2022-11-01),
9. 11283005 - Spacer scheme and method for MRAM (2022-03-22),
10. 11139200 - Multi-layer structure having a dense middle layer (2021-10-05),
11. 10879456 - Sidewall spacer stack for magnetic tunnel junctions (2020-12-29),
12. 10748765 - Multi-layer mask and method of forming same (2020-08-18),
13. 10510586 - Multi-layer structure having a dense middle layer (2019-12-17),
14. 8669641 - Diffusion region routing for narrow scribe-line devices (2014-03-11),
15. 7968431 - Diffusion region routing for narrow scribe-line devices (2011-06-28),

Title: Inventor Chin Kun Lan: Revolutionizing Technology in Hsinchu

Introduction: Chin Kun Lan is a pioneering inventor based in Hsinchu, Taiwan, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Chin Kun Lan holds several patents in various technological domains, including advancements in semiconductor manufacturing processes, renewable energy systems, and artificial intelligence algorithms.

Career Highlights: With a career spanning over two decades, Chin Kun Lan has worked with leading tech companies and research institutions in Taiwan, playing a key role in developing cutting-edge technologies that have reshaped industries.

Collaborations: Throughout his career, Chin Kun Lan has collaborated with top engineers, scientists, and researchers globally, fostering a culture of innovation and knowledge exchange to drive forward technological advancements.

Conclusion: Chin Kun Lan's relentless pursuit of innovation and his passion for pushing the boundaries of technology continue to inspire the next generation of inventors and innovators in Hsinchu and beyond.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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