The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 26, 2023

Filed:

Jun. 05, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Joung-Wei Liou, Zhudong Town, TW;

Chin Kun Lan, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76832 (2013.01); H01L 21/0228 (2013.01); H01L 21/02178 (2013.01); H01L 21/02205 (2013.01); H01L 21/02274 (2013.01); H01L 21/76877 (2013.01); H01L 23/5329 (2013.01);
Abstract

The present disclosure relates to a method of forming a semiconductor structure. The method includes depositing an etch-stop layer (ESL) over a first dielectric layer. The ESL layer deposition can include: flowing a first precursor over the first dielectric layer; purging at least a portion of the first precursor; flowing a second precursor over the first dielectric layer to form a sublayer of the ESL layer; and purging at least a portion of the second precursor. The method can further include depositing a second dielectric layer on the ESL layer and forming a via in the second dielectric layer and through the ESL layer.


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