The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2019

Filed:

Sep. 07, 2018
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Joung-Wei Liou, Zhudong Town, TW;

Chin Kun Lan, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/033 (2006.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76816 (2013.01); H01L 21/0228 (2013.01); H01L 21/02126 (2013.01); H01L 21/02211 (2013.01); H01L 21/02274 (2013.01); H01L 21/0332 (2013.01); H01L 21/0337 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/32136 (2013.01); H01L 21/32139 (2013.01); H01L 21/76877 (2013.01); H01L 21/7684 (2013.01); H01L 21/76847 (2013.01);
Abstract

An embodiment is a method of fabricating a semiconductor structure. The method includes depositing a hard mask. A multi-layer structure is deposited over the hard mark. The multi-layer structure includes a bottom layer, a first middle layer over the bottom layer, a second middle layer over the first middle layer, and a top layer over the second middle layer. The first middle layer comprises a SiCHOmaterial in which the SiCHOmaterial has a silicon-to-silicon bond content in a range from about 0.5% to about 5%. The multi-layer structure is patterned to form a patterned first middle layer having openings. The hard mask is etched through the openings in the patterned first middle layer.


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