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For the Inventor, By the Inventor

Kaohsiung, Taiwan

Chih Cheng Lee

This inventor holds 11 USPTO granted patents. Top assignee: Advanced Semiconductor Engineering, Inc.. Active years: 2018-2023.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chih Cheng Lee. Retrieved from https://idiyas.com/inventor/chih-cheng-lee-99x52oip

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 11

% Patents Active = 100.0

Average Co-Inventor Count = 1.8

ph-index = 2

Forward Citations = 48(Granted Patents)


Company Filing History:

goldMedal11 out of 1,968 
 
Advanced Semiconductor Engineering, Inc.
 patents

Years Active: 2018-2023

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11 patents (USPTO):Explore Patents
1. 11715694 - Embedded component package structure having a magnetically permeable layer (2023-08-01),
2. 11276660 - Semiconductor device package having a core substrate and an embedded component in the core substrate (2022-03-15),
3. 11232993 - Semiconductor device package and method of manufacturing the same (2022-01-25),
4. 11062996 - Embedded component package structure and manufacturing method thereof (2021-07-13),
5. 10748843 - Semiconductor substrate including embedded component and method of manufacturing the same (2020-08-18),
6. 10424547 - Semiconductor device package and a method of manufacturing the same (2019-09-24),
7. 10340212 - Semiconductor package structure having a heat dissipation structure (2019-07-02),
8. 10332757 - Semiconductor device package having a multi-portion connection element (2019-06-25),
9. 10096542 - Substrate, semiconductor package structure and manufacturing process (2018-10-09),
10. 10074602 - Substrate, semiconductor package structure and manufacturing process (2018-09-11),
11. 9887167 - Embedded component package structure and method of manufacturing the same (2018-02-06),

Title: Chih Cheng Lee: Innovator in Semiconductor Packaging

Introduction

Chih Cheng Lee is a prominent inventor based in Kaohsiung, Taiwan. He has made significant contributions to the field of semiconductor packaging, holding a total of 11 patents. His innovative work has advanced the technology used in electronic devices, making them more efficient and reliable.

Latest Patents

One of his latest patents is for an embedded component package structure that includes a magnetically permeable layer. This semiconductor device package features a top surface and a bottom surface, with a first conductive element integrated into the magnetically permeable layer. Additionally, it includes a first conductive via that extends from the top surface into the layer, ensuring electrical connectivity while being separated from the magnetically permeable layer. Another notable patent involves a semiconductor device package that contains an electronic component surrounded by a first passivation layer and a conductive layer with a rough surface. This design enhances the performance and durability of semiconductor devices.

Career Highlights

Chih Cheng Lee is currently employed at Advanced Semiconductor Engineering, Inc., where he continues to push the boundaries of semiconductor technology. His work has not only contributed to the company's success but has also positioned him as a leader in the field of semiconductor packaging.

Collaborations

Throughout his career, Chih Cheng Lee has collaborated with talented individuals such as Hsing Kuo Tien and Yu-Lin Shih. These partnerships have fostered innovation and have led to the development of groundbreaking technologies in semiconductor packaging.

Conclusion

Chih Cheng Lee's contributions to semiconductor packaging are noteworthy and impactful. His innovative patents and collaborations reflect his dedication to advancing technology in the electronics industry. His work continues to influence the future of semiconductor devices, ensuring they meet the demands of modern technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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