Chew Hoe Ang

This inventor holds 20 USPTO granted patents, primarily in Semiconductor Fabrication. Top assignees: Chartered Semiconductor Manufacturing Ltd (Corporation), Advanced Micro Devices Corporation. Active years: 2002-2010.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chew Hoe Ang. Retrieved from https://idiyas.com/inventor/chew-hoe-ang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

USPTO Granted Patents = 20

% Patents Active = 60.0

Average Co-Inventor Count = 3.8

ph-index = 9

Forward Citations = 349(Granted Patents)

Company Filing History:

19 out of 962

Chartered Semiconductor Manufacturing Ltd (Corporation)

patents

1 out of 13,185

Advanced Micro Devices Corporation

patents

Years Active: 2002-2010

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Areas of Expertise:

High-K Dielectrics

CMOS Devices

Gate Structures

Capacitor Applications

Shallow Trench Isolation

Asymmetrical Memory Devices

Triple Gate Oxide

Epitaxial Growth

Ion Implantation

Thermal Instability Testing

Charge Storage Devices

20 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 7795046 - Method and apparatus for monitoring endcap pullback (2010-09-14),

2. 7562318 - Test structure for automatic dynamic negative-bias temperature instability testing (2009-07-14),

3. 7479425 - Method for forming high-K charge storage device (2009-01-20),

4. 7326609 - Semiconductor device and fabrication method (2008-02-05),

5. 7202140 - Method to fabricate Ge and Si devices together for performance enhancement (2007-04-10),

6. 7176094 - Ultra-thin gate oxide through post decoupled plasma nitridation anneal (2007-02-13),

7. 7103861 - Test structure for automatic dynamic negative-bias temperature instability testing (2006-09-05),

8. 7095073 - High K artificial lattices for capacitor applications to use in Cu or Al BEOL (2006-08-22),

9. 7022625 - Method of fabricating a gate dielectric layer with reduced gate tunnelling current and reduced boron penetration (2006-04-04),

10. 6841441 - Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing (2005-01-11),

11. 6830971 - High K artificial lattices for capacitor applications to use in CU or AL BEOL (2004-12-14),

12. 6762085 - Method of forming a high performance and low cost CMOS device (2004-07-13),

13. 6743291 - Method of fabricating a CMOS device with integrated super-steep retrograde twin wells using double selective epitaxial growth (2004-06-01),

14. 6734082 - Method of forming a shallow trench isolation structure featuring a group of insulator liner layers located on the surfaces of a shallow trench shape (2004-05-11),

15. 6670248 - Triple gate oxide process with high-k gate dielectric (2003-12-30),

Title: Inventor Spotlight: Chew Hoe Ang

Introduction

Chew Hoe Ang is a prominent inventor based in Singapore, renowned for his contributions to the field of semiconductor technology. With an impressive portfolio of 20 patents, he continues to push boundaries and innovate in his area of expertise.

Latest Patents

Among his latest inventions is a method and apparatus for monitoring endcap pullback. This invention outlines several apparatus and methods designed to monitor endcap pullback effectively. One innovative aspect includes a substrate that has multiple semiconductor regions, each equipped with a transistor. These transistors are connected to a voltage source, allowing the levels of currents flowing through them to indicate the positions of the gates concerning their borders.

Another significant patent revolves around a test structure for automatic dynamic negative-bias temperature instability testing. This invention presents a novel structure and process for conducting automatic dynamic stress testing on PMOS devices, specifically for Negative Bias Temperature Instability (NBTI). The structure comprises an integrated inverter, two electronic switches for mode switching, and a PMOS FET device under test, ensuring accurate testing while isolating the test device during characterization.

Career Highlights

Chew Hoe Ang has had a significant impact on the semiconductor industry through his work at renowned companies such as Chartered Semiconductor Manufacturing Ltd and Advanced Micro Devices Corporation. His experience in these leading organizations has facilitated his innovative advancements in semiconductor technologies.

Collaborations

Throughout his career, Chew Hoe Ang has collaborated with esteemed colleagues, including Jia Zhen Zheng and Eng Hua Lim. Together, they have worked on various projects, reflecting a commitment to excellence in research and development within the semiconductor field.

Conclusion

With 20 patents to his name, Chew Hoe Ang has established himself as a leading inventor in Singapore’s semiconductor industry. His latest inventions demonstrate his dedication to innovation and the importance of collaboration in driving technological advancements. As he continues his work, he remains a vital contributor to the evolving landscape of semiconductor technology.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]