The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2003
Filed:
Aug. 07, 2002
Chartered Semiconductor Manufacturing Ltd., Singapore, SG;
Abstract
A method for forming, on a semiconductor substrate, a dielectric layer having a variable thickness and composition. The dielectric layer so formed can be used to form electronic devices such as MOSFETS and CMOSFETS that require gate dielectrics of different thicknesses. On a silicon substrate in accord with the preferred embodiment, the method requires the formation of three regions, two with SiO layers of different thicknesses and a third region of substrate with no oxide. A final thin layer of high-k dielectric is formed covering the three regions, so that the region with no oxide has the thinnest dielectric layer of only high-k material and the other two regions have the high-k dielectric over SiO layers of different thickness. A final layer of gate electrode material can be formed and patterned to form the required device structure.