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For the Inventor, By the Inventor

Hsinchu, Taiwan

Cheng-Lin Huang

This inventor holds 107 USPTO granted patents and 2 published patent applications, primarily in Chip Package Structure (CPC class H01L24-11). Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., Other. Active years: 2004-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Cheng-Lin Huang. Retrieved from https://idiyas.com/inventor/cheng-lin-huang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 107 

% Patents Active = 81.3

Average Co-Inventor Count = 3.7

ph-index = 12

Forward Citations = 684(Granted Patents)

Forward Citations (Not Self Cited) = 652(Dec 10, 2025)


Inventors with similar research interests:

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Location History:

  • Taipei, TW (2004 - 2007)
  • Hsinchu, TW (2005 - 2024)

Company Filing History:

goldMedal106 out of 42,810 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents
silverMedal1 out of 834,453 
Other
 patents

Years Active: 2004-2026

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Areas of Expertise:
Chip Package Structure
Fan-Out Feature
Semiconductor Die
Through Vias
Metal Oxide Layered Structure
Conductive External Connector
Wafer Packaging
Bump Layout
Air-Gap Region
Singulation
Multiple Gradients
Conductive Features
107 patents (USPTO):Explore Patents
1. 12635484 - Metal oxide layered structure and methods of forming the same (2026-05-19),
2. 12489045 - Package structure with through vias (2025-12-02),
3. 12381114 - Package structure with fan-out feature (2025-08-05),
4. 12255173 - Chip package structure (2025-03-18),
5. 12183709 - Chip package structure with ring-like structure (2024-12-31),
6. 12087618 - Method for forming semiconductor die having edge with multiple gradients (2024-09-10),
7. 11948876 - Package structure with through vias (2024-04-02),
8. 11855039 - Chip package structure (2023-12-26),
9. 11854826 - Metal oxide layered structure and methods of forming the same (2023-12-26),
10. 11848302 - Chip package structure with ring-like structure (2023-12-19),
11. 11784091 - Structure and formation method of chip package with fan-out feature (2023-10-10),
12. 11569159 - Structure and formation method of chip package with through vias (2023-01-31),
13. 11545463 - Chip package structure with ring-like structure (2023-01-03),
14. 11532577 - Fan-out package and methods of forming thereof (2022-12-20),
15. 11527504 - Conductive external connector structure and method of forming (2022-12-13),

Title: Cheng-Lin Huang: Pioneering Innovator in Hsinchu

Introduction: Cheng-Lin Huang has carved a path of innovation and excellence in the field of invention, inspiring countless inventors and shaping the technological landscape. With a remarkable 101 patents to his name, he continues to push boundaries and redefine industry standards from his base in Hsinchu, Taiwan.

Latest Patents: Among his latest patents, Cheng-Lin Huang has introduced groundbreaking package structures with through vias, enhancing the efficiency and functionality of semiconductor chips. These innovations showcase his commitment to advancing technology through inventive solutions.

Career Highlights: Cheng-Lin Huang's career is studded with achievements at prominent companies like Taiwan Semiconductor Manufacturing Company Limited (TSMC), where his expertise has significantly contributed to the company's success. His dedication to research and development has resulted in numerous cutting-edge patents that have revolutionized the semiconductor industry.

Collaborations: Throughout his career, Cheng-Lin Huang has collaborated with esteemed coworkers such as Jing-Cheng Lin and Shin-Puu Jeng, pooling their collective knowledge and skills to drive innovation forward. These partnerships have further solidified his standing as a trailblazer in the world of technology.

Conclusion: Cheng-Lin Huang's relentless pursuit of innovation and his unwavering dedication to excellence have cemented his legacy as a pioneer in the field of invention. His impact will continue to resonate for years to come, inspiring future generations of inventors to push boundaries and transform the technological landscape.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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