The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2023

Filed:

Aug. 05, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Sheng-Yao Yang, Hsinchu, TW;

Ling-Wei Li, Hsinchu, TW;

Yu-Jui Wu, Hsinchu, TW;

Cheng-Lin Huang, Hsinchu, TW;

Chien-Chen Li, Hsinchu, TW;

Lieh-Chuan Chen, Hsinchu, TW;

Che-Jung Chu, Hsinchu, TW;

Kuo-Chio Liu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 24/81 (2013.01); H01L 21/76816 (2013.01); H01L 21/76871 (2013.01); H01L 24/09 (2013.01); H01L 24/11 (2013.01); H01L 24/17 (2013.01); H01L 24/30 (2013.01);
Abstract

A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump.


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