logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12087618 B1

PDFFull Text
Date of Patent:
Sep. 10, 2024

Filed:

Apr. 15, 2021

Method for forming semiconductor die having edge with multiple gradients

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yu-Sheng Tang, Hsinchu, TW;

Fu-Chen Chang, Hsinchu, TW;

Cheng-Lin Huang, Hsinchu, TW;

Wen-Ming Chen, Zhunan Township, Miaoli County, TW;

Chun-Yen Lo, Hsinchu, TW;

Kuo-Chio Liu, Hsinchu, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;

Attorney:

McClure, Qualey & Rodack, LLP

Primary Examiner:

Brian Turner

Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/304 (2006.01); H01L 21/67 (2006.01); H01L 21/683 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 23/58 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76802 (2013.01); H01L 21/304 (2013.01); H01L 21/3043 (2013.01); H01L 21/67011 (2013.01); H01L 21/67092 (2013.01); H01L 21/67132 (2013.01); H01L 21/6836 (2013.01); H01L 21/78 (2013.01); H01L 23/48 (2013.01); H01L 23/481 (2013.01); H01L 24/11 (2013.01); H01L 24/32 (2013.01); H01L 23/49816 (2013.01); H01L 23/562 (2013.01); H01L 23/585 (2013.01); H01L 25/0657 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01);
Abstract

A method for sawing a semiconductor wafer is provided. The method includes sawing the semiconductor wafer with a first dicing blade to form a first opening. The semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape. The first opening is formed in the upper portion of the substrate. The method also includes sawing the semiconductor wafer with a second dicing blade from the first opening to form a second opening under the first opening and in the middle portion of the substrate. The method further includes sawing the semiconductor wafer with a third dicing blade from the second opening to form a third opening under the second opening and penetrating the lower portion of the substrate, so that the semiconductor wafer is divided into two dies. The first dicing blade, the second dicing blade, and the third dicing blade have different widths.

Find Patent Forward Citations

Loading…