Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Cheng-Lin Huang

Jing-Cheng Lin

Shin-Puu Jeng

Jung-Hua Chang

Ching-Hua Hsieh

Ling-Wei Li

Wen-Ming Chen

Shau-Lin Shue

Chen-Hua Douglas Yu

Po-Hao Tsai

Kuo-Chio Liu

Jui-Pin Hung

Nai-Wei Liu

Chun-Yen Lo

Shing-Chyang Pan

Fu-Chen Chang

Shang-Yun Hou

Mong-Song Liang

Dian-Hau Chen

Cheng-Chieh Hsieh

Chin-Fu Kao

Yuh-Jier Mii

Che-Jung Chu

Hsien-Ming Lee

Kuo-Ching Hsu

Szu Wei Lu

Hsien-Wen Liu

Zhen-Cheng Wu

Li-Lin Su

Chien-Chen Li

Shu-Hui Su

Meng-Fu Shih

Chin-Yu Ku

Chien-Ming Huang

Wei-Chih Huang

Lieh-Chuan Chen

Jiing-Feng Yang

Yu-Nu Hsu

Te-Hsun Pang

Yu-Jui Wu

Wan-Ting Shih

Chen-Hsun Liu

Chien-Pin Chan

Chi-Hung Lin

Jy-Jie Gau

Yuan-Fu Liu

Yung-Chiuan Cheng

Sheng-Yao Yang

Wen-Chih Chiou

Po-Yao Lin

Ying-Ching Shih

Chao-Hsien Peng

Shyue-Ter Leu

Yu-Sheng Tang

Ying Ching Shih

Ren-Guei Wu

Shu-Shen Yeh

Po-Hsiang Huang

Chin-Hua Wang

Hsin-Yu Chen

Yung-Chih Wang

Meng-Liang Lin

Wen-Yi Lin

Kuang-Chun Lee

Fang Wen Tsai

Yan-Fu Lin

Winston Shue

I-Ting Chen

Ya-Hsi Hwung

Shao-Lin Shue

Hsien-Wei Chen

Chung-Shi Liu

Ming-Da Cheng

Li-Jui Chen

Ming-Chih Yew

Mei Sheng Zhou

Meng-Tse Chen

Weng-Jin Wu

Chung-Long Chang

Chii-Ping Chen

Chun-Hsien Lin

Yu-Liang Lin

Henry Lo

Hsiu-Mei Yu

Shih Ting Lin

Yu-Huan Chen

Ai-Sen Liu

Pin-Yi Hsin

Shih-Yen Chen

Min-Tar Liu

Chih-Chao Shih

Wei-An Tsao

Ruei-Yi Tsai

Gorge Huang

Tony Lu

Gnesh Yeh

Candy Liang

Sunny Su

Fu-Kang Chiao

Shih Che Wang

A package structure is provided. The package structure includes a conductive structure having a first portion with a first sidewall and a second portion with a second sidewall, and the first sidewall and the second sidewall have different slopes. The package structure also includes a semiconductor chip beside the conductive structure and a protective layer laterally surrounding the conductive structure and the semiconductor chip. The protective layer covers the first sidewall of the first portion and the second sidewall of the second portion. The protective layer is made of a polymer material dispersed with fillers.

Package structure with through vias

A package structure includes a first semiconductor die having a first conductive pad and a second semiconductor die having a second conductive pad. The package structure also includes a conductive structure and a third semiconductor die. The third semiconductor die extends across a portions of the first semiconductor die and the second semiconductor die. A third conductive pad and a fourth conductive pad of the third semiconductor die are aligned with the first conductive pad and the second conductive pad, respectively. The package structure further includes a protective layer surrounding the conductive structure and the third semiconductor die and an insulating layer extending across an interface between the protective layer and the conductive structure. The package structure includes a conductive layer electrically connected to the conductive structure. The conductive layer has a first portion spaced from the conductive structure and a second portion directly above the conductive structure.

Package structure with fan-out feature

A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a barrier layer over a surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer. The conductive pad has a first portion passing through the insulating layer and the barrier layer and connected to the conductive via structure. The chip package structure includes a conductive bump over the conductive pad. The chip package structure includes a second substrate. The chip package structure includes an underfill layer between the first substrate and the second substrate.

Chip package structure

A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive ring-like structure over and electrically insulated from the chip. The conductive ring-like structure surrounds a central region of the chip. The chip package structure includes a first solder structure over the conductive ring-like structure. The first solder structure and the conductive ring-like structure are made of different materials.

Chip package structure with ring-like structure

A method for sawing a semiconductor wafer is provided. The method includes sawing the semiconductor wafer with a first dicing blade to form a first opening. The semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape. The first opening is formed in the upper portion of the substrate. The method also includes sawing the semiconductor wafer with a second dicing blade from the first opening to form a second opening under the first opening and in the middle portion of the substrate. The method further includes sawing the semiconductor wafer with a third dicing blade from the second opening to form a third opening under the second opening and penetrating the lower portion of the substrate, so that the semiconductor wafer is divided into two dies. The first dicing blade, the second dicing blade, and the third dicing blade have different widths.

Method for forming semiconductor die having edge with multiple gradients

A package structure is provided. The package structure includes a conductive structure having a first portion and a second portion, and the second portion is wider than the first portion. The package structure also includes a semiconductor chip laterally separated from the conductive structure. The package structure further includes a protective layer laterally surrounding the conductive structure and the semiconductor chip. The first portion of the conductive structure has a sidewall extending from the second portion to a surface of the protective layer. The protective layer laterally surrounds an entirety of the sidewall of the first portion.

A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a barrier layer over a surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer and having a first portion and a second portion. The chip package structure includes a conductive bump over the second portion of the conductive pad. A third portion of the conductive pad is between the conductive bump and the conductive via structure from a top view of the conductive pad, the conductive bump, and the conductive via structure.

Some embodiment structures and methods are described. A structure includes an integrated circuit die at least laterally encapsulated by an encapsulant, and a redistribution structure on the integrated circuit die and encapsulant. The redistribution structure is electrically coupled to the integrated circuit die. The redistribution structure includes a first dielectric layer on at least the encapsulant, a metallization pattern on the first dielectric layer, a metal oxide layered structure on the metallization pattern, and a second dielectric layer on the first dielectric layer and the metallization pattern. The metal oxide layered structure includes a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, and a thickness of the metal oxide layered structure is at least 50 Å. The second dielectric layer is a photo-sensitive material. The metal oxide layered structure is disposed between the metallization pattern and the second dielectric layer.

Metal oxide layered structure and methods of forming the same

A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive bump over and electrically connected to the chip. The chip package structure includes a ring-like structure over and electrically insulated from the chip. The ring-like structure surrounds the conductive bump, and the ring-like structure and the conductive bump are made of a same material.

A package structure and a formation method of a package structure are provided. The method includes forming a conductive structure over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes forming a protective layer to surround the conductive structure and the semiconductor die. The method further includes forming an insulating layer over the protective layer. The insulating layer has an opening exposing a portion of the conductive structure. In addition, the method includes forming a conductive layer over the insulating layer. The conductive layer fills the opening, and the conductive layer has a substantially planar top surface.

Structure and formation method of chip package with fan-out feature

A package structure and a formation method of a package structure are provided. The method includes forming a conductive structure over a carrier substrate. The conductive structure has a lower portion and an upper portion, and the upper portion is wider than the lower portion. The method also includes disposing a semiconductor die over the carrier substrate. The method further includes forming a protective layer to surround the conductive structure and the semiconductor die. In addition, the method includes forming a conductive bump over the conductive structure. The lower portion of the conductive structure is between the conductive bump and the upper portion of the conductive structure.

Structure and formation method of chip package with through vias

A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump.

An embodiment is a method including depositing a first dielectric layer over a molding compound and a chip and patterning a first opening in the first dielectric layer to expose a contact of the chip. A first metallization layer is deposited over the first dielectric layer and in the first opening, where a portion of the first metallization layer in the first opening has a flat top. A second dielectric layer is deposited over the first metallization layer and the first dielectric layer. A second metallization layer is deposited in a second opening in the second dielectric layer, where the second metallization layer does not have a flat top within the second opening.

Fan-out package and methods of forming thereof

External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.

Conductive external connector structure and method of forming

A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a chip over a first surface of the first substrate. The chip package structure includes a barrier layer over a second surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer and passing through the insulating layer and the barrier layer to connect with the conductive via structure. The chip package structure includes a conductive bump over the conductive pad.

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Hsinchu, Taiwan

Cheng-Lin Huang