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For the Inventor, By the Inventor

Kanata, Canada

Atul Katoch

This inventor holds 91 USPTO granted patents and 15 published patent applications and 2 EPO patents, primarily in Memory Device Innovation (CPC class G11C11-419). Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., Nxp B.v., Koninklijke Philips Corporation N.v.. Active years: 2007-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Atul Katoch. Retrieved from https://idiyas.com/inventor/atul-katoch

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 91 

% Patents Active = 82.4

 

Average Co-Inventor Count = 1.8

ph-index = 5

Forward Citations = 203(Granted Patents)

Forward Citations (Not Self Cited) = 159(Dec 10, 2025)


Inventors with similar research interests:

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Location History:

  • Eindhoven, NL (2007 - 2008)
  • Ontario, CA (2012)
  • Kanata, CA (US) (2015)
  • Hsinchu, TW (2020 - 2021)
  • Kanata, CA (2009 - 2024)

Company Filing History:

goldMedal86 out of 42,965 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents
silverMedal3 out of 5,336 
 
Nxp B.v.
 patents
bronzeMedal2 out of 21,919 
 
Koninklijke Philips Corporation N.v.
 patents

Years Active: 2007-2026

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Areas of Expertise:
Memory Device
Power Management
High-Speed Memory
SRAM Architecture
Bit Line Precharge
Clock Generation
Comparator Circuit
Signal Edge Sharpening
Negative Bit Line Generation
Wake Up Mechanisms
Testing Architectures
Voltage Control
91 patents (USPTO):Explore Patents
1. 12770663 - Semiconductor memory device with controlled bit line pre-charging and method of operating the same (2026-10-20),
2. 12665004 - Sensing circuit of memory device and control method of sensing circuit (2026-06-23),
3. 12512150 - Memory device with global and local latches (2025-12-30),
4. 12436858 - Scan synchronous-write-through testing architectures for a memory device (2025-10-07),
5. 12400690 - Global boosting circuit (2025-08-26),
6. 12374386 - Variable voltage bit line precharge (2025-07-29),
7. 12361991 - Far end driver for memory clock (2025-07-15),
8. 12340869 - Low power wake up for memory (2025-06-24),
9. 12327586 - Bit line pre-charge circuit for power management modes in multi bank SRAM (2025-06-10),
10. 12322474 - Memory device, read clock generation circuit, and method for controlling read operation in memory device (2025-06-03),
11. 12315552 - Word line delay interlock circuit for write operation (2025-05-27),
12. 12277991 - Memory device with reset voltage control (2025-04-14),
13. 12272427 - Semiconductor device including first and second clock generators (2025-04-08),
14. 12243602 - Method, device, and circuit for high-speed memories (2025-03-04),
15. 12190944 - Memory device with signal edge sharpener circuitry (2025-01-07),

Title: The Innovative Journey of Atul Katoch

Introduction: Atul Katoch, a visionary inventor hailing from Kanata, Canada, has made significant contributions to the field of technology through his groundbreaking innovations.

Latest Patents: Atul Katoch's recent patents include cutting-edge advancements in artificial intelligence algorithms for autonomous vehicles, revolutionizing the way we perceive transportation safety and efficiency.

Career Highlights: With a career spanning over two decades, Atul Katoch has held key positions in leading tech companies, driving research and development initiatives that have led to numerous successful patent applications.

Collaborations: Atul Katoch has collaborated with top research institutions and universities worldwide, fostering a culture of innovation and knowledge sharing that has propelled the industry forward.

Conclusion: Atul Katoch's relentless pursuit of innovation and his passion for pushing the boundaries of technology make him a true trailblazer in the world of inventions. His work continues to inspire future generations of inventors to think boldly and create fearlessly.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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