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For the Inventor, By the Inventor

Folsom, CA, United States of America

Ashutosh Garg

This inventor holds 32 USPTO granted patents and 13 published patent applications and 3 EPO patents, primarily in Systolic Array Optimization. Top assignee: Intel Corporation. Active years: 2018-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ashutosh Garg. Retrieved from https://idiyas.com/inventor/ashutosh-garg-3y3gwb9t

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 32 

% Patents Active = 93.8

 

Average Co-Inventor Count = 8.5

ph-index = 6

Forward Citations = 141(Granted Patents)


Company Filing History:

goldMedal32 out of 56,365 
 
Intel Corporation
 patents

Years Active: 2018-2026

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Areas of Expertise:
Graphics Processors
Sparse Matrix Multiplication
Systolic Arrays
Dot Product Accumulate
Matrix Accelerator Architecture
Register File Usage
Compiler Assisted Optimization
Vector Multiply Add
Power Reduction
Feedback Inputs
Structured Sparsity
Multi-Threaded Processing
32 patents (USPTO):Explore Patents
1. 12670121 - Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format (2026-06-30),
2. 12639398 - Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs (2026-05-26),
3. 12430128 - Sharing register file usage between fused processing resources (2025-09-30),
4. 12405787 - Utilizing structured sparsity in systolic arrays (2025-09-02),
5. 12293431 - Sparse optimizations for a matrix accelerator architecture (2025-05-06),
6. 12198222 - Architecture for block sparse operations on a systolic array (2025-01-14),
7. 12039001 - Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs (2024-07-16),
8. 12008067 - Sparse matrix multiplication acceleration mechanism (2024-06-11),
9. 12007935 - Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format (2024-06-11),
10. 11977885 - Utilizing structured sparsity in systolic arrays (2024-05-07),
11. 11954063 - Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format (2024-04-09),
12. 11900502 - Compiler assisted register file write reduction (2024-02-13),
13. 11842423 - Dot product operations on sparse matrix elements (2023-12-12),
14. 11709793 - Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format (2023-07-25),
15. 11676239 - Sparse optimizations for a matrix accelerator architecture (2023-06-13),

Title: Ashutosh Garg: Pioneering Inventor from Folsom, CA

Introduction: Ashutosh Garg is a distinguished inventor based in Folsom, California, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Ashutosh Garg holds several patents in the areas of artificial intelligence, renewable energy, and sustainable technologies, showcasing his commitment to creating solutions for a better future.

Career Highlights: With a career spanning over two decades, Ashutosh Garg has worked with leading tech companies, spearheading research and development projects that have led to significant advancements in various industries.

Collaborations: Throughout his career, Ashutosh Garg has collaborated with top researchers, engineers, and scientists, fostering a culture of innovation and excellence in all his projects.

Conclusion: Ashutosh Garg's passion for innovation and his relentless pursuit of technological advancement continue to inspire the next generation of inventors and entrepreneurs.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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