The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2024

Filed:

Nov. 16, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Subramaniam Maiyuran, Gold River, CA (US);

Mathew Nevin, Fair Oaks, CA (US);

Jorge Parra, El Dorado Hills, CA (US);

Ashutosh Garg, Folsom, CA (US);

Shubra Marwaha, Santa Clara, CA (US);

Shubh Shah, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/16 (2006.01); G06F 7/487 (2006.01); G06F 9/30 (2018.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 17/16 (2013.01); G06F 7/4876 (2013.01); G06F 9/3001 (2013.01); G06F 9/30036 (2013.01); G06F 13/1673 (2013.01); G06F 2207/3892 (2013.01);
Abstract

An apparatus to facilitate acceleration of matrix multiplication operations. The apparatus comprises a systolic array including matrix multiplication hardware to perform multiply-add operations on received matrix data comprising data from a plurality of input matrices and sparse matrix acceleration hardware to detect zero values in the matrix data and perform one or more optimizations on the matrix data to reduce multiply-add operations to be performed by the matrix multiplication hardware.


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