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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12198222 B1

PDFFull Text
Date of Patent:
Jan. 14, 2025

Filed:

Dec. 07, 2023

Architecture for block sparse operations on a systolic array

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Abhishek Appu, El Dorado Hills, CA (US);

Subramaniam Maiyuran, Gold River, CA (US);

Mike Macpherson, Portland, OR (US);

Fangwen Fu, Folsom, CA (US);

Jiasheng Chen, El Dorado Hills, CA (US);

Varghese George, Folsom, CA (US);

Vasanth Ranganathan, El Dorado Hills, CA (US);

Ashutosh Garg, Folsom, CA (US);

Joydeep Ray, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Jefferson Watson Mendonsa & Hamilton LLP

Primary Examiner:

Shawn Doman

Int. Cl.
CPC ...
G06F 17/16 (2006.01); G06F 7/544 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/50 (2006.01); G06F 12/0806 (2016.01); G06F 15/80 (2006.01); G06N 3/048 (2023.01); G06N 3/08 (2023.01); G06N 3/084 (2023.01); G06T 1/20 (2006.01);
U.S. Cl.
CPC ...
G06T 1/20 (2013.01); G06F 7/5443 (2013.01); G06F 9/30036 (2013.01); G06F 9/3887 (2013.01); G06F 9/3888 (2023.08); G06F 9/38885 (2023.08); G06F 9/5027 (2013.01); G06F 12/0806 (2013.01); G06F 15/8046 (2013.01); G06F 17/16 (2013.01); G06N 3/048 (2023.01); G06N 3/08 (2013.01); G06N 3/084 (2013.01);
Abstract

Embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides for data aware sparsity via compressed bitstreams. One embodiment provides for block sparse dot product instructions. One embodiment provides for a depth-wise adapter for a systolic array.

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