The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 13, 2023
Filed:
Jun. 03, 2021
Intel Corporation, Santa Clara, CA (US);
Joydeep Ray, Folsom, CA (US);
Scott Janus, Loomis, CA (US);
Varghese George, Folsom, CA (US);
Subramaniam Maiyuran, Gold River, CA (US);
Altug Koker, El Dorado Hills, CA (US);
Abhishek Appu, El Dorado Hills, CA (US);
Prasoonkumar Surti, Folsom, CA (US);
Vasanth Ranganathan, El Dorado Hills, CA (US);
Andrei Valentin, San Jose, CA (US);
Ashutosh Garg, Folsom, CA (US);
Yoav Harel, Carmichael, CA (US);
Arthur Hunter, Jr., Cameron Park, CA (US);
SungYe Kim, Folsom, CA (US);
Mike Macpherson, Portland, OR (US);
Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US);
William Sadler, Folsom, CA (US);
Lakshminarayanan Striramassarma, Folsom, CA (US);
Vikranth Vemulapalli, Folsom, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.