The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 07, 2024
Filed:
Nov. 30, 2020
Intel Corporation, Santa Clara, CA (US);
Subramaniam Maiyuran, Gold River, CA (US);
Jorge Parra, El Dorado Hills, CA (US);
Ashutosh Garg, Folsom, CA (US);
Chandra Gurram, Folsom, CA (US);
Chunhui Mei, San Diego, CA (US);
Durgesh Borkar, Folsom, CA (US);
Shubra Marwaha, Folsom, CA (US);
Supratim Pal, Bangalore, IN;
Varghese George, Folsom, CA (US);
Wei Xiong, Fremont, CA (US);
Yan Li, San Diego, CA (US);
Yongsheng Liu, San Diego, CA (US);
Dipankar Das, Pune, IN;
Sasikanth Avancha, Kolar District, IN;
Dharma Teja Vooturi, Jagtial, IN;
Naveen K. Mellempudi, Bangalore, IN;
INTEL CORPORATION, Santa Clara, CA (US);
Abstract
An apparatus to facilitate utilizing structured sparsity in systolic arrays is disclosed. The apparatus includes a processor comprising a systolic array to receive data from a plurality of source registers, the data comprising unpacked source data, structured source data that is packed based on sparsity, and metadata corresponding to the structured source data; identify portions of the unpacked source data to multiply with the structured source data, the portions of the unpacked source data identified based on the metadata; and output, to a destination register, a result of multiplication of the portions of the unpacked source data and the structured source data.