Arvind Nembili Veeravalli

This inventor holds 8 USPTO granted patents. Top assignees: Cadence Design Systems, Inc., Texas Instruments Corporation. Active years: 2011-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Arvind Nembili Veeravalli. Retrieved from https://idiyas.com/inventor/arvind-nembili-veeravalli

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 8

% Patents Active = 100.0

Average Co-Inventor Count = 4.4

ph-index = 3

Forward Citations = 21(Granted Patents)

Location History:

Karnataka, IN (2018)
Bengaluru, IN (2011 - 2022)

Company Filing History:

5 out of 2,619

Cadence Design Systems, Inc.

patents

3 out of 29,888

Texas Instruments Corporation

patents

Years Active: 2011-2025

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8 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12475286 - System and method for comparing circuit design constraint sets (2025-11-18),

2. 12332304 - System and method for automatic fault detection in an electronic design (2025-06-17),

3. 11455450 - System and method for performing sign-off timing analysis of electronic circuit designs (2022-09-27),

4. 10114920 - Method and apparatus for performing sign-off timing analysis of circuit designs using inter-power domain logic (2018-10-30),

5. 9881123 - Method and system for timing analysis with adaptive timing window optimization for determining signal integrity impact (2018-01-30),

6. 8296701 - Method for designing a semiconductor device based on leakage current estimation (2012-10-23),

7. 8255850 - Fabricating IC with NBTI path delay within timing constraints (2012-08-28),

8. 8051399 - IC design flow incorporating optimal assumptions of power supply voltage drops at cells when performing timing analysis (2011-11-01),

Title: Innovations by Arvind Nembili Veeravalli

Introduction

Arvind Nembili Veeravalli is a prominent inventor based in Bengaluru, India. He has made significant contributions to the field of electronic design automation, holding a total of seven patents. His work focuses on improving the efficiency and reliability of electronic circuit designs through innovative methods and systems.

Latest Patents

One of his latest patents is titled "System and method for automatic fault detection in an electronic design." This invention involves a method for automatic detection during timing analysis. It includes reading design and power intent information associated with an electronic design and automatically identifying a plurality of inter-power domain paths. The system further filters these paths to identify faulty ones using a graph-based approach and generates a report depicting the identified issues.

Another notable patent is "System and method for performing sign-off timing analysis of electronic circuit designs." This invention addresses dynamic voltage and frequency scaling (DVFS) based timing signoff in an electronic design environment. It allows users to specify voltage sweeps for each power net and automatically generates DVFS configurations based on the specified parameters.

Career Highlights

Arvind has worked with leading companies in the industry, including Cadence Design Systems, Inc. and Texas Instruments Corporation. His experience in these organizations has contributed to his expertise in electronic design automation and patent development.

Collaborations

Throughout his career, Arvind has collaborated with notable professionals, including Naresh Kumar and Palkesh Jain. These collaborations have further enhanced his innovative capabilities and contributions to the field.

Conclusion

Arvind Nembili Veeravalli is a distinguished inventor whose work in electronic design automation has led to several impactful patents. His innovative approaches continue to shape the future of electronic circuit design.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]