The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 27, 2022
Filed:
Jun. 03, 2021
Cadence Design Systems, Inc., San Jose, CA (US);
Sushobhit Singh, Noida, IN;
Arvind Nembili Veeravalli, Bangalore, IN;
Naresh Kumar, Noida, IN;
Beenish, Agra, IN;
Mahesh Diwakar Sadhankar, Noida, IN;
Ankit Sethi, Delhi, IN;
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Embodiments include herein are directed towards a method for dynamic voltage and frequency scaling (DVFS) based timing signoff associated with an electronic design environment. Embodiments may include receiving, using a processor, an electronic design and specifying, via a graphical user interface, a voltage sweep for each power net associated with the electronic design. Embodiments may further include specifying, via the graphical user interface, at least one voltage sweep to be excluded from analysis. Embodiments may also include automatically generating DVFS configurations based upon, at least in part, the voltage sweep for each power net and the at least one voltage sweep to be excluded from analysis.