Cadence Design Systems, Inc.

Texas Instruments Corporation

Arvind Nembili Veeravalli

Naresh Kumar

Palkesh Jain

Sushobhit Singh

Ajoy Mandal

Igor Keller

Prashant Sethia

Venkatraman Ramakrishnan

Umesh Gupta

Manuj Verma

Ratnakar Goyal

Ramamurthy Vishweshwara

Ritika Govila

Sarath Jayalath Kirihennedige

Ankit Sethi

Venkatasubramanyam Visvanathan

Shashank Tripathi

Saulius Kersulis

Beenish

H Udayakumar

Mahesh Diwakar Sadhankar

Daksh Bakshi

Mahesh D Sadhankar

Embodiments included herein are directed towards a method for comparing constraint sets. The embodiments may include determining, using at least one processor, at least one arrival propagation time corresponding to at least one endpoint, the at least one endpoint associated with a first constraint set and a second constraint set. The embodiments may further include creating, using the at least one processor, a first tag associated with the first constraint set and a second tag associated with the second constraint set. The embodiments may also include determining, using the at least one processor, at least one of: a non-equivalent path exception corresponding to the at least one endpoint and based at least in part on at least one of the arrival propagation time, the first tag, and the second tag; and an equivalent path exception corresponding to the at least one endpoint.

System and method for comparing circuit design constraint sets

Embodiments include herein are directed towards a method for automatic detection during a timing analysis. Embodiments may include reading, using a processor, design and power intent information associated with an electronic design and automatically identifying a plurality of inter-power domain paths from the design and power intent information. Embodiments may further include automatically filtering the plurality of inter-power domain paths to identify one or more faulty inter-power domain paths using a graph-based approach and automatically generating a report depicting the one or more faulty inter-power domain paths.

System and method for automatic fault detection in an electronic design

Embodiments include herein are directed towards a method for dynamic voltage and frequency scaling (DVFS) based timing signoff associated with an electronic design environment. Embodiments may include receiving, using a processor, an electronic design and specifying, via a graphical user interface, a voltage sweep for each power net associated with the electronic design. Embodiments may further include specifying, via the graphical user interface, at least one voltage sweep to be excluded from analysis. Embodiments may also include automatically generating DVFS configurations based upon, at least in part, the voltage sweep for each power net and the at least one voltage sweep to be excluded from analysis.

System and method for performing sign-off timing analysis of electronic circuit designs

A netlist of a multiple voltage circuit design having a plurality of power domains is established, then inter-power domain (IPD) paths traversing the circuit design are identified, according to whether they traverse multi-supply elements, or are clock paths capturing such a path. The netlist is then pruned to disable or remove cells or stages not traversed by an IPD path. A timing analyzer conducts a multi-domain timing analysis of the IPD timing paths in the pruned IPD netlist. Thereby, the circuit design is thoroughly tested according to the applicable ranges of voltage conditions without excessive runtime.

Method and apparatus for performing sign-off timing analysis of circuit designs using inter-power domain logic

A method and system are provided for timing analysis of an electronic circuit design. A timing graph defines a plurality of timing paths through different subsections of the electronic circuit design. A timing window is defined for each of the nodes included in a timing path. At least one preliminary round of a predetermined signal integrity analysis is executed on the circuit design based on the timing windows to identify at least one pair of crosstalk-coupled victim and aggressor nodes. Each victim node's timing window is adaptively adjusted according to a predetermined timing property thereof. At least one primary round of the predetermined signal integrity analysis is executed on the electronic circuit design based in part on this adaptively adjusted timing window for each victim node to generate a delay, which is annotated to the timing graph. A predetermined static timing analysis is executed based on the delay-annotated timing graph.

Method and system for timing analysis with adaptive timing window optimization for determining signal integrity impact

A method of designing a semiconductor device includes preparing a first design for a semiconductor device and estimating leakage current for the first design. The method also includes determining a leakage current cumulative distribution function (CDF) for the first design. The method further includes preparing a second design for the semiconductor device based on determination of the leakage current CDF for the first design. Further, the method includes estimating leakage current for the second design. The method also includes determining a leakage current CDF for the second design in accordance to the determination of the leakage current CDF for the first design. Moreover, the method includes selecting one of the first design and the second design based on a comparison of the leakage current CDF for the first design and the leakage CDF for the second design.

Method for designing a semiconductor device based on leakage current estimation

According to an aspect of the present invention, statistical timing analysis is applied with respect to a stress degradation that occurs in fabricated integrated circuits (IC) when used for a long duration. The circuit design may be suitably modified to account for the degradations (e.g., those caused by NBTI and CHC for transistors, those caused due to electromigration in case of interconnects). As a result, the fabricated ICs may be less susceptible to such degradations. The features are extended to model complex circuit blocks and also account for different degrees of stress that different circuit blocks are subjected to, in a same age of operation.

Fabricating IC with NBTI path delay within timing constraints

An aspect of the present invention selects a maximum voltage and a minimum voltage in respective sub-intervals of a timing window in which an output of a cell is expected to switch, and performing timing analysis based on the selected maximum voltage and the selected minimum voltage. By using appropriate smaller sub-intervals within the timing window, more optimal physical layout of the design may be obtained. In an embodiment, the sub-intervals equal a cell delay, i.e., a delay between an input change to an output change for a corresponding cell. According to another aspect of the present invention, the sub-interval for later cells in a timing path are modified based on a modified timing window of previous cells in the timing path, to reduce the computational requirement.

IC design flow incorporating optimal assumptions of power supply voltage drops at cells when performing timing analysis

Growing community of inventors

Bengaluru, India

Arvind Nembili Veeravalli