The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 30, 2018
Filed:
Jun. 29, 2016
Cadence Design Systems, Inc., San Jose, CA (US);
Umesh Gupta, Noida, IN;
Shashank Tripathi, Ghaziabad, IN;
Naresh Kumar, Greater Noida, IN;
Arvind Nembili Veeravalli, Bangalore, IN;
Prashant Sethia, Noida, IN;
Ritika Govila, Gurgaon, IN;
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A netlist of a multiple voltage circuit design having a plurality of power domains is established, then inter-power domain (IPD) paths traversing the circuit design are identified, according to whether they traverse multi-supply elements, or are clock paths capturing such a path. The netlist is then pruned to disable or remove cells or stages not traversed by an IPD path. A timing analyzer conducts a multi-domain timing analysis of the IPD timing paths in the pruned IPD netlist. Thereby, the circuit design is thoroughly tested according to the applicable ranges of voltage conditions without excessive runtime.