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For the Inventor, By the Inventor

Noida, India

Umesh Gupta

USPTO Granted Patents = 8

Average Co-Inventor Count = 5.6

ph-index = 5

Forward Citations = 104(Granted Patents)


Location History:

  • Kurukshetra, IN (2017)
  • Uttar Pradesh, IN (2014 - 2018)
  • Noida, IN (2018 - 2022)

Company Filing History:

goldMedal8 out of 2,545 
 
Cadence Design Systems, Inc.
 patents

Years Active: 2014-2025

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8 patents (USPTO):Explore Patents
1. 12423504 - Adaptive path based analysis process (2025-09-23),
2. 11531803 - IPBA-driven full-depth EPBA of operational timing for circuit design (2022-12-20),
3. 10915685 - Circuit stage credit based approaches to static timing analysis of integrated circuits (2021-02-09),
4. 10776547 - Infinite-depth path-based analysis of operational timing for circuit design (2020-09-15),
5. 10114920 - Method and apparatus for performing sign-off timing analysis of circuit designs using inter-power domain logic (2018-10-30),
6. 9875333 - Comprehensive path based analysis process (2018-01-23),
7. 9589096 - Method and apparatus for integrating spice-based timing using sign-off path-based analysis (2017-03-07),
8. 8863052 - System and method for generating and using a structurally aware timing model for representative operation of a circuit design (2014-10-14),

Title: Umesh Gupta: Innovator in Electronic Design Automation

Introduction

Umesh Gupta is a prominent inventor based in Noida, India. He has made significant contributions to the field of electronic design automation, holding a total of 8 patents. His work focuses on improving the efficiency and accuracy of digital circuit design processes.

Latest Patents

One of Umesh Gupta's latest patents is the "Adaptive path based analysis process." This invention relates to a system and method for electronic design automation. It includes loading various libraries, netlists, or constraints associated with an electronic design, as well as parasitic data. The process involves performing a self-adaptive, infinite depth, path-based analysis on portions of the electronic design, ultimately leading to a more thorough analysis based on this innovative approach.

Another notable patent is the "IPBA-driven full-depth EPBA of operational timing for circuit design." This static timing analysis system is designed to identify and report timing violations in digital circuit designs before fabrication. It utilizes exhaustive path-based analysis informed by infinite-depth path-based analysis to provide comprehensive results. This method reduces pessimism and enhances the completeness of design analysis compared to conventional systems.

Career Highlights

Umesh Gupta is currently employed at Cadence Design Systems, Inc., where he continues to develop cutting-edge solutions in electronic design automation. His expertise and innovative mindset have positioned him as a key player in the industry.

Collaborations

Umesh has collaborated with talented coworkers, including Naresh Kumar and Prashant Sethia, contributing to various projects that enhance the capabilities of electronic design tools.

Conclusion

Umesh Gupta's contributions to electronic design automation through his patents and work at Cadence Design Systems, Inc. highlight his role as an influential inventor in the field. His innovative approaches continue to shape the future of digital circuit design.

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