The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2018

Filed:

Jan. 19, 2016
Applicant:

Cadence Design Sysems, Inc., San Jose, CA (US);

Inventors:

Sourabh Kumar Verma, Uttar Pradesh, IN;

Naresh Kumar, Uttar Pradesh, IN;

Ajay Tomar, Delhi, IN;

Rakesh Agarwal, Delhi, IN;

Umesh Gupta, Uttar Pradesh, IN;

Manish Bansal, Delhi, IN;

Kaustav Guha, Uttar Pradesh, IN;

Prashant Sethia, Uttar Pradesh, IN;

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5081 (2013.01); G06F 17/5031 (2013.01);
Abstract

The present disclosure relates to a system and method for electronic design automation. Embodiments may include receiving, using at least one processor, an electronic design and determining one or more graph based analysis ('GBA') violating nodes associated with the electronic design. Embodiments may include identifying a non-covered violating node from the GBA violating nodes and determining a worst timing path through the non-covered violating node. Embodiments may further include invoking a path-based analysis ('PBA') on the worst timing path and determining if the worst timing path satisfies the PBA analysis.


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