Palo Alto, CA, United States of America

Rakesh Agarwal

USPTO Granted Patents = 11 

 

Average Co-Inventor Count = 2.6

ph-index = 5

Forward Citations = 110(Granted Patents)


Location History:

  • Palo Alto, CA (US) (2001 - 2022)
  • Delhi, IN (2018 - 2022)

Company Filing History:


Years Active: 2001-2022

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11 patents (USPTO):

Title: Rakesh Agarwal: Innovator in Circuit Design and Virtual Machine Integrity

Introduction

Rakesh Agarwal is a prominent inventor based in Palo Alto, California, known for his significant contributions to circuit design and virtual machine technology. With a total of 11 patents to his name, Agarwal has made notable advancements in the fields of static timing analysis and memory protection mechanisms.

Latest Patents

One of Agarwal's latest patents is titled "IPBA-driven full-depth EPBA of operational timing for circuit design." This invention presents a static timing analysis system that identifies and reports timing violations in digital circuit designs before fabrication. It utilizes exhaustive path-based analysis (EPBA) informed by infinite-depth path-based analysis (IPBA) to deliver comprehensive analysis results. This approach contrasts with conventional EPBA systems, which may terminate after reaching a maximum depth to avoid prolonged runtimes. The system functions effectively for both hold-mode and setup-mode analysis, achieving reduced pessimism compared to methods using IPBA alone, while providing a more thorough analysis than those relying solely on EPBA.

Another significant patent by Agarwal involves "Techniques for protecting memory pages of a virtual computing instance." This invention outlines mechanisms to safeguard the integrity of memory within a virtual machine. By leveraging the capabilities of the hypervisor, the system monitors writes to the virtual machine's memory pages. A guest integrity driver communicates with the hypervisor to request this functionality, ensuring additional protections against malicious software. These protections include an elevated execution mode, known as 'integrity mode,' which can only be accessed from a specified entry point.

Career Highlights

Throughout his career, Rakesh Agarwal has worked with notable companies such as VMware, Inc. and Cadence Design Systems, Inc. His experience in these organizations has contributed to his expertise in circuit design and virtual machine technologies.

Collaborations

Agarwal has collaborated with talented individuals in the industry, including Naresh Kumar and Umesh Gupta. These partnerships have likely enhanced his innovative capabilities and contributed to his successful patent portfolio.

Conclusion

Rakesh Agarwal's work in circuit design and virtual machine integrity showcases his innovative spirit and technical expertise. His contributions continue to influence the fields of technology and engineering, making him a noteworthy inventor in today's landscape.

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