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Kanagawa, Japan

Semiconductor Leading Edge Technologies, Inc.

USPTO Granted Patents = 17

% Expired Patents = 35.3

Forward Citations = 173

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19 inventors (with patents filed for the assignee):

Kenji Tokunaga (2 out of 16 patents)

Hisaharu Seita (2 out of 4 patents)

Hiroki Arai (1 out of 16 patents)

4. Takayuki Ohba (1 out of 14 patents)

5. Ichiro Okabe (1 out of 2 patents)

6. Kazuyoshi Torii (1 out of 28 patents)

7. Satoshi Kume (1 out of 2 patents)

8. Riichirou Mitsuhashi (1 out of 1 patent)

9. Atsushi Horiuchi (1 out of 1 patent)

10. Jeong Yeal Kim (1 out of 1 patent)

11. Yoshimasa Kawase (1 out of 1 patent)

12. Tetsuro Hanawa (1 out of 1 patent)

13. Osamu Koike (1 out of 1 patent)

14. Akira Mitsuiki (1 out of 1 patent)

15. Toshiaki Tsutsumi (1 out of 1 patent)

17 patents: Sort by Forward Citations

1. 6992013 - Method of forming a fine pattern using a silicon-oxide-based film, semiconductor device with a silicon-oxide-based film and method of manufacture thereof (2006-01-31),

2. 6943899 - Substrate-container measuring device, and substrate-container measuring jig (2005-09-13),

3. 6881657 - Semiconductor device and method for manufacturing semiconductor device (2005-04-19),

4. 6880563 - Apparatus and method of cleaning a substrate (2005-04-19),

5. 6875971 - Wafer edge exposure apparatus, and wafer edge exposure method (2005-04-05),

6. 6817822 - Load port, wafer processing apparatus, and method of replacing atmosphere (2004-11-16),

7. 6808352 - Method for transporting boards, load port apparatus, and board transport system (2004-10-26),

8. 6769908 - Wafer heat-treatment system and wafer heat-treatment method (2004-08-03),

9. 6731375 - Projection aligner, exposing method and semiconductor device (2004-05-04),

10. 6726799 - Plasma etching apparatus with focus ring and plasma etching method (2004-04-27),

11. 6716761 - Method of forming fine patterns (2004-04-06),

12. 6535781 - Apparatus for modifying coordinates (2003-03-18),

13. 6473996 - Load port system for substrate processing system, and method of processing substrate (2002-11-05),

14. 6446645 - Dip cleaning system for a substrate, system for evaluating the amount of particles and method of evaluating the amount of particles adhering to a substrate (2002-09-10),

15. 6379219 - Chemical mechanical polishing machine and chemical mechanical polishing method (2002-04-30),

Company Overview

Semiconductor Leading Edge Technologies, Inc. (SLET) is a prominent player in the semiconductor industry, specializing in the development and manufacturing of advanced semiconductor technologies. The company focuses on cutting-edge research in areas such as lithography, etching, and deposition processes, which are essential for producing high-performance integrated circuits. Based in Kanagawa, Japan, SLET plays a critical role in supporting the global semiconductor supply chain, contributing to innovations that drive various technology sectors.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 20 2026

17 Patents

#106 in Kanagawa

#3,230 in Japan

#35,948 in the World

Kanagawa, Japan

Semiconductor Leading Edge Technologies, Inc.

Forward Citations = 173

19 inventors:

Kenji Tokunaga (2 out of 16 patents)

Hisaharu Seita (2 out of 4 patents)

Hiroki Arai (1 out of 16 patents)

4. Takayuki Ohba (1 out of 14 patents)

5. Ichiro Okabe (1 out of 2 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Semiconductor Leading Edge Technologies, Inc.. Retrieved from https://idiyas.com/company/semiconductor-leading-edge-technologies

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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