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For the Inventor, By the Inventor

San Jose, CA, United States of America

Netspeed Systems

USPTO Granted Patents = 74

% Expired Patents = 37.8

Forward Citations = 1,083

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19 inventors (with patents filed for the assignee):

goldMedal Sailesh Kumar (72 out of 90 patents)

silverMedal Eric Norige (33 out of 38 patents)

bronzeMedal Joji Philip (22 out of 29 patents)

4.  Joseph Rowlands (12 out of 13 patents)

5.  Pier Giorgio Raponi (11 out of 14 patents)

6.  Sundari Mitra (11 out of 12 patents)

7.  Mahmud Hassan (11 out of 11 patents)

8.  Joe Rowlands (9 out of 10 patents)

9.  Nishant Rao (8 out of 13 patents)

10.  Anup Gangwar (5 out of 17 patents)

11.  Vishnu Mohan Pusuluri (5 out of 6 patents)

12.  Poonacha Kongetira (4 out of 5 patents)

13.  Rajesh Chopra (3 out of 10 patents)

14.  James Bauman (3 out of 9 patents)

15.  Rimu Kaushal (3 out of 3 patents)


Core Competencies:
Network-On-Chip
SoC Integration
Power Management
Latency Optimization
QoS Allocation
Traffic Management
Heterogeneous Channels
Buffer Sizing
Automatic Topology Generation
Congestion Control
Machine Learning
Virtual Routers

74 patents:

1. 11176302 - System on chip (SoC) builder (2021-11-16),
2. 11144457 - Enhanced page locality in network-on-chip (NoC) architectures (2021-10-12),
3. 11023377 - Application mapping on hardened network-on-chip (NoC) of field-programmable gate array (FPGA) (2021-06-01),
4. 10983910 - Bandwidth weighting mechanism based network-on-chip (NoC) configuration (2021-04-20),
5. 10896476 - Repository of integration description of hardware intellectual property for NoC construction and SoC integration (2021-01-19),
6. 10749811 - Interface virtualization and fast path for Network on Chip (2020-08-18),
7. 10735335 - Interface virtualization and fast path for network on chip (2020-08-04),
8. 10613616 - Systems and methods for facilitating low power on a network-on-chip (2020-04-07),
9. 10564704 - Systems and methods for facilitating low power on a network-on-chip (2020-02-18),
10. 10564703 - Systems and methods for facilitating low power on a network-on-chip (2020-02-18),
11. 10554496 - Heterogeneous SoC IP core placement in an interconnect to optimize latency and interconnect performance (2020-02-04),
12. 10547514 - Automatic crossbar generation and router connections for network-on-chip (NOC) topology generation (2020-01-28),
13. 10528682 - Automatic performance characterization of a network-on-chip (NOC) interconnect (2020-01-07),
14. 10523599 - Buffer sizing of a NoC through machine learning (2019-12-31),
15. 10218581 - Generation of network-on-chip layout based on user specified topological constraints (2019-02-26),
Company Overview
Netspeed Systems, based in San Jose, CA, specializes in advanced Network-On-Chip (NoC) technologies that enhance the integration and performance of System-on-Chip (SoC) designs. The company focuses on optimizing power management, reducing latency, and improving Quality of Service (QoS) allocation within complex chip architectures. Their innovative solutions address critical challenges in traffic management and buffer sizing, enabling efficient communication across heterogeneous channels in modern semiconductor applications.
Profile summary synthesized from public USPTO records and patent filings.

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USPTO Data Jan 1 1976 - Oct 20 2026

74 Patents

#145 in San Jose, CA

#1,175 in California

#4,982 in US

#10,140 in the World

San Jose, CA (US)
San Jose, CA, United States of America

Netspeed Systems

Forward Citations = 1,083

19 inventors:

goldMedal Sailesh Kumar (72 out of 90 patents)

silverMedal Eric Norige (33 out of 38 patents)

bronzeMedal Joji Philip (22 out of 29 patents)

4.  Joseph Rowlands (12 out of 13 patents)

5.  Pier Giorgio Raponi (11 out of 14 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Netspeed Systems. Retrieved from https://idiyas.com/company/netspeed-systems

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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