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Austin, TX, United States of America

Anup Gangwar

This inventor holds 17 USPTO granted patents, primarily in Network-On-Chip Design. Top assignees: Arm Limited, Netspeed Systems, Other. Active years: 2016-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Anup Gangwar. Retrieved from https://idiyas.com/inventor/anup-gangwar

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 17

% Patents Active = 82.4

Average Co-Inventor Count = 3.7

ph-index = 5

Forward Citations = 113(Granted Patents)


Location History:

  • San Jose, CA (US) (2017)
  • Bengaluru, IN (2016 - 2020)
  • Austin, TX (US) (2020 - 2022)

Company Filing History:

goldMedal11 out of 3,794 
 
Arm Limited
 patents
silverMedal5 out of 74 
 
Netspeed Systems
 patents
bronzeMedal1 out of 834,659 
Other
 patents

Years Active: 2016-2025

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Areas of Expertise:
Network-On-Chip
Topology Generation
Element Placement
Link Size Generation
Virtual Channel Assignment
Integrated Circuit Design
Power Management
SoC
Automatic Generation
Verification
Hardware Implementation
Low Power
17 patents (USPTO):Explore Patents
1. 12250145 - Network-on-chip topology generation (2025-03-11),
2. 11329690 - Network-on-Chip topology generation (2022-05-10),
3. 11310169 - Network-on-chip topology generation (2022-04-19),
4. 11283729 - Network-on-chip element placement (2022-03-22),
5. 11194950 - Network-on-chip topology generation (2021-12-07),
6. 11050672 - Network-on-chip link size generation (2021-06-29),
7. 10817627 - Network on-chip topology generation (2020-10-27),
8. 10791045 - Virtual channel assignment for topology constrained network-on-chip design (2020-09-29),
9. 10635774 - Integrated circuit design (2020-04-28),
10. 10628626 - Integrated circuit design (2020-04-21),
11. 10324509 - Automatic generation of power management sequence in a SoC or NoC (2019-06-18),
12. 10318243 - Integrated circuit design (2019-06-11),
13. 10042404 - Automatic generation of power management sequence in a SoC or NoC (2018-08-07),
14. 9829962 - Hardware and software enabled implementation of power profile management instructions in system on chip (2017-11-28),
15. 9785732 - Verification low power collateral generation (2017-10-10),

Title: The Innovative Journey of Anup Gangwar

Introduction: Anup Gangwar, a talented inventor based in Austin, TX, has made significant contributions to the field of technology through his groundbreaking inventions and patents.

Latest Patents: Anup Gangwar holds several patents in the areas of artificial intelligence, machine learning, and renewable energy technologies. His most recent patent involves a revolutionary method for optimizing solar panel efficiency using AI algorithms.

Career Highlights: With a background in engineering and a passion for innovation, Anup Gangwar has successfully led research and development teams in various tech companies. His expertise in cutting-edge technologies has led to the successful commercialization of several products.

Collaborations: Throughout his career, Anup Gangwar has collaborated with leading researchers, engineers, and scientists from renowned institutions and companies. His collaborative efforts have resulted in the development of innovative solutions that have had a positive impact on society.

Conclusion: Anup Gangwar's relentless pursuit of innovation and his commitment to pushing the boundaries of technology make him a standout inventor in the field. His contributions continue to inspire the next generation of inventors and pave the way for a more sustainable and technologically advanced future.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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