The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 11, 2025

Filed:

Mar. 16, 2022
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Nitin Kumar Agarwal, Bangalore, IN;

Anup Gangwar, Austin, TX (US);

Honnahuggi Harinath Venkata Naga Ambica Prasad, Bangalore, IN;

Ravishankar Sreedharan, Bangalore, IN;

Narayana Sri Harsha Gade, Bangalore, IN;

Assignee:

Arm Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 45/00 (2022.01); H04L 45/02 (2022.01); H04L 45/24 (2022.01); H04L 45/42 (2022.01);
U.S. Cl.
CPC ...
H04L 45/38 (2013.01); H04L 45/02 (2013.01); H04L 45/24 (2013.01); H04L 45/42 (2013.01);
Abstract

A computer-based method and system for synthesizing a Network-on-Chip (NoC) is provided. One method includes determining physical data, device data, bridge data, traffic data and domain data based on an input specification for the NoC; assigning a domain to each bridge port; partitioning each traffic flow into one of a plurality of bins based on the bridge port domain assignments and the domain crossing constraints; creating a virtual node at each bridge port endpoint; generating a candidate topology for each bin based on the physical data, the device data, the bridge data, the traffic data, the domain data and the virtual nodes, each candidate topology including bridge ports, a tree of routers, routes and connections; and generating a final topology by merging the candidate topologies.


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